CS2000-OTP

DS758PP1

3

6.3 Global Configuration Parameters ................................................................................................... 25

6.3.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 25

6.3.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 25

6.3.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 25

6.3.4 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 25

6.3.5 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 26

6.3.6 M2 Pin Configuration (M2Config[2:0]) ................................................................................... 26

6.3.7 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 26

7. CALCULATING THE USER DEFINED RATIO .................................................................................... 27

7.1 High Resolution 12.20 Format ....................................................................................................... 27

7.2 High Multiplication 20.12 Format ................................................................................................... 27

8. PROGRAMMING INFORMATION ........................................................................................................ 28

9. PACKAGE DIMENSIONS .................................................................................................................... 29

THERMAL CHARACTERISTICS ......................................................................................................... 29

10. ORDERING INFORMATION .............................................................................................................. 30

11. REVISION HISTORY .......................................................................................................................... 30

LIST OF FIGURES

Figure 1. Typical Connection Diagram ........................................................................................................ 5

Figure 2. Delta-Sigma Fractional-N Frequency Synthesizer .......................................................................8

Figure 3. Hybrid Analog-Digital PLL ............................................................................................................ 9

Figure 4. Fractional-N Source Selection Overview ..................................................................................... 9

Figure 5. Internal Timing Reference Clock Divider ................................................................................... 10

Figure 6. External Component Requirements for Crystal Circuit .............................................................. 11

Figure 7. CLK_IN removed for > 223 SysClk cycles ................................................................................. 12

Figure 8. CLK_IN removed for < 223 SysClk cycles but > tCS ................................................................. 12

Figure 9. CLK_IN removed for < tCS ........................................................................................................ 13

Figure 10. Low bandwidth and new clock domain .................................................................................... 13

Figure 11. High bandwidth with CLK_IN domain re-use ........................................................................... 14

Figure 12. Ratio Feature Summary ........................................................................................................... 18

Figure 13. PLL Clock Output Options ....................................................................................................... 19

Figure 14. Auxiliary Output Selection ........................................................................................................ 19

Figure 15. M2 Mapping Options ................................................................................................................ 20

Figure 16. Parameter Configuration Sets .................................................................................................. 23

LIST OF TABLES

Table 1. Modal and Global Configuration .................................................................................................. 10

Table 2. Ratio Modifier .............................................................................................................................. 15

Table 3. Automatic Ratio Modifier ............................................................................................................. 15

Table 4. Example Audio Oversampling Clock Generation from CLK_IN .................................................. 16

Table 5. Example 12.20 R-Values ............................................................................................................ 27

Table 6. Example 20.12 R-Values ............................................................................................................ 27