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AT89C5115-RATUM 数据表(PDF) 68 Page - ATMEL Corporation |
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AT89C5115-RATUM 数据表(HTML) 68 Page - ATMEL Corporation |
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68 / 113 page ![]() 68 AT89C5115 4128G–8051–02/08 Watchdog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 49. Machine Cycle Count To compute WD Timeout, the following formula is applied: Note: Svalue represents the decimal value of (S2 S1 S0) Find Hereafter computed Timeout values for fOSCXTAL = 12 MHz in X1 mode Table 50. Timeout Computation S2 S1 S0 Machine Cycle Count 0 0 0 214 - 1 0 0 1 215 - 1 0 1 0 216 - 1 0 1 1 217 - 1 1 0 0 218 - 1 1 0 1 219 - 1 1 1 0 220 - 1 1 1 1 221 - 1 S2 S1 S0 fOSC=12 MHz fOSC=16MHz fOSC=20 MHz 0 0 0 16.38 ms 12.28 ms 9.82 ms 0 0 1 32.77 ms 24.57 ms 19.66 ms 0 1 0 65.54 ms 49.14 ms 39.32 ms 0 1 1 131.07 ms 98.28 ms 78.64 ms 1 0 0 262.14 ms 196.56 ms 157.28 ms 1 0 1 524.29 ms 393.12 ms 314.56 ms 1 1 0 1.05 s 786.24 ms 629.12 ms 1 1 1 2.10 s 1.57 s 1.25 s FTime Out F o sc 6 2 × WD X 2 X 2 ∧ 2 14 2 Sva lu e × ( ) ----------------------------------------------------------------------------- = – |
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