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AT89C5115-RATUM 数据表(PDF) 17 Page - ATMEL Corporation |
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AT89C5115-RATUM 数据表(HTML) 17 Page - ATMEL Corporation |
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17 / 113 page  17 AT89C5115 4128G–8051–02/08 Register Table 11. CKCON Register CKCON (S:8Fh) Clock Control Registe r Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = x000 0000b 7 6 5 4 3 2 1 0 - WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2 Bit Number Bit Mnemonic Description 7 - Reserved Do not set this bit. 6 WDX2 Watchdog Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PCAX2 Programmable Counter Array Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 4 SIX2 Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3 T2X2 Timer 2 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 2 T1X2 Timer 1 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 1 T0X2 Timer 0 Clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 0 X2 CPU Clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the individual peripherals ’X2’ bits. |
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