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AT89C5115-RATUM 数据表(PDF) 92 Page - ATMEL Corporation |
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AT89C5115-RATUM 数据表(HTML) 92 Page - ATMEL Corporation |
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92 / 113 page  92 AT89C5115 4128G–8051–02/08 Figure 44. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Reset Value = xxxx x000b bit addressable 7 6 5 4 3 2 1 0 - - - - - - EADC - Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 EADC ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. 0 - Reserved The value read from this bit is indeterminate. Do not set this bit. |
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