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6237A–DRMSD–29-May-06

ATSAM3703

9.1.2

IO Status Register

• TE: Transmit empty

If 0, data from ATSAM3703 to host is pending and IRQ is high. Reading the data at A0 = 0 sets

TE to 1 and clear IRQ.

• RF: Receiver full

If 0, then ATSAM3703 is ready to accept DATA from host.

Note:

If status bit RF is not checked by host, write cycle time should not be lower than 3 µs.

9.2

SmartMedia and Other Peripheral Interfaces

This is a master 8-bit parallel interface, allowing connection to SmartMedia or other peripherals

such as LCD screens.

Pins used:

• I/O7 - I/O0 (I/O)

• SMPD (input)

•SMCE, SMALE, SMCLE, SMRE, SMWE (outputs)

All these pins are fully under firmware control, therefore timing compatibility is ensured by firm-

ware only.

9.3

Serial Slave Synchronous Interface

The SAM3303 can be controlled by an external host processor through the unidirectional serial

interface. However, no firmware can be downloaded at power-up through this interface. There-

fore an external ROM/Flash/EEPROM is required.

Pins used:

• SCLK, SYNC, SDIN (input)

•INT (output)

Data is shifted MSB first. The IC samples an incoming SDIN bit on the rising edge of SCLK,

therefore the host should change SDIN on the negative SCLK edge.

SYNC allows initial synchronization. The rising edge of SYNC, which should occur with SCLK

low, indicates that SDIN holds MSB data on the next rising SCLK.

The data is stored internally into a 256 bytes FIFO.

When the FIFO count is below 64, the INT output goes low. This allows the host processor to

send data in burst mode.

t

PWR

WR pulse width

50

-

-

ns

t

DWS

Write data setup time

10

-

-

ns

Write data hold time

0.9

-

-

ns

Table 9-1.

Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

TE

RF

X

X

X

X

X

X

Status register is read when A0 = 1, RD = 0, CS = 0