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6237A–DRMSD–29-May-06

ATSAM3703

9.4.3

Single Data Rate SDRAM

9.4.3.1

Memory Size

The data bus is 4 bits wide. Due to the 12-bit address bus, the maximum accessible address

space is 128 Mbits (32M x 4). Larger components are supported, but only a part of the address

space is used.

9.4.3.2

Pinning

Table 9-7.

Timing Requirements

Symbol

Parameter

Value

Skew between WDQS, WD3, WD2, WD1 and WD0

max 1.6 ns

t

DQSCK

Delay from WCK, WCK to WDQS (excluding CAS latency)

max 5 ns

Table 9-8.

SDR SDRAM Memory Size

DDR Size

Bank

Address

Row

Address

Column

Address

Remark

64 Mbits (16M x 4)

2 bits

12 bits

10 bits

128 Mbits (32M x 4)

2 bits

12 bits

11 bits

256 Mbits (64M x 4)

2 bits

13 bits

11 bits

Only 12-bit rows are used (only 128 Mbits are

accessible)

512 Mbits (128M x 4)

2 bits

13 bits

12 bits

Table 9-9.

SDR Pinning

ATSAM3703 Pin

SDR Pin

Description

-

A13, A12

Unused address bits (for larger device). Must be tied to zero.

WA11..WA0

A11..A0

Address

WBA1, WBA0

BA1, BA0

Bank address

WD3..WD0

DQ3..DQ0

Data

WDQS

-

Not used. Must be left unconnected.

DM

Data mask. Must be tied to zero.

WCK

CK

Clock

WCK

-

Not used. Must be left unconnected.

WCKE

CKE

Clock enable

-CS

Chip select. Must be tied to zero.

WCAS

CAS

Command

WRAS

RAS

WWE

WE

VREF

-

Must be connected to VC25/2.