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6237A–DRMSD–29-May-06

ATSAM3703

The maximum SCLK frequency is f

The minimum time between two bytes is 64 f

The contents of the SDIN data are defined by the firmware.

Figure 9-3.

Typical Interface Timing for Serial Slave

9.4

External DDR SDRAM and SDRAM Memories

9.4.1

Overview

The ATSAM3703 supports the DDR SDRAM components compatible with JEDEC standard

(JESD79D).

Following memories can be connected to the ATSAM3703:

• DDR SDRAM, 4 bits wide

• SDRAM, 4 bits wide

DDR SDRAM and SDRAM cannot be connected at the same time. The type of connection is

SSTL_2 for DDR SDRAM and LVTTL for SDRAM.

DDR SDRAM and SDRAM use time multiplexed addressing with a ROW/COL scheme (banks

WBA0 to WBA1 and address lines WA0 to WA11).

9.4.2

Double Data Rate SDRAM

9.4.2.1

Memory Size

The data bus is 4 bits wide. Due to the 12-bit address bus, the maximum accessible address

space is 128 Mbits (32M x 4). Larger components are supported, but only a part of the address

space is used.

SCLK

SYNC

SDIN

MSB

Table 9-2.

DDR SDRAM Memory Size

DDR Size

Bank

Address

Row

Address

Column

Address

Remark

64 Mbits (16 M x 4)

2 bits

12 bits

10 bits

128 Mbits (32 M x 4)

2 bits

12 bits

11 bits

256 Mbits (64 M x 4)

2 bits

13 bits

11 bits

Only 12-bit rows are used (only 128 Mbits are accessible).

512 Mbits (128 M x 4)

2 bits

13 bits

12 bits

1 Gbits (256 M x4)

2 bits

14 bits

12 bits

Only 12-bit rows are used (only 128 Mbits are accessible).

value; see below)