CoreAI

v2.0

11

Note that after an APB read of the interrupt status registers has been performed, each INT[14:0] bit will be cleared if

its condition is no longer valid. If an APB read of the interrupt status registers has just occurred coincident with a

pending interrupt condition, the interrupt condition will have priority in order to prevent a missed

interrupt.

Table 9 • CoreAI Internal Register Address Map*

PADDR[4:0]

Type

Reset Value

Brief Description

0x00

R/W

0x04

ACM Control/Status Register (low-order)

0x01

R/W

0x00

ACM Control/Status Register (high-order)

0x02

R/W

0x00

ACM Address Register

0x03

–

0x00

Reserved

0x04

R/W

0x00

ACM Data Register

0x05

–

0x00

Reserved

0x06

R/W

0x00

ADC Control Register 1 (low-order)

0x07

R/W

0x00

ADC Control Register 1 (high-order)

0x08

R/W

0x00

ADC Control Register 2 (low-order)

0x09

R/W

0x00

ADC Control Register 2 (high-order)

0x0a

R/W

0x00

ADC Control Register 3 (low-order)

0x0b

R/W

0x00

ADC Control Register 3 (high-order)

0x0c

R/W

0x00

ADC Control Register 4 (low-order)

0x0d

R/W

0x00

ADC Control Register 4 (high-order)

0x0e

R/W

0x00

ADC Control Register 5 (low-order)

0x0f

R/W

0x00

ADC Control Register 5 (high-order)

0x10

R

0x00

ADC Status Register (low-order)

0x11

R

0x00

ADC Status Register (high-order)

0x12

R

0x00

Read FIFO Data Output

0x13

–

0x00

Reserved

0x14

R

0x0c

Read FIFO Status

0x15

–

0x00

Reserved

0x16

R/W

0x00

Interrupt Enable Register (low-order)

0x17

R/W

0x00

Interrupt Enable Register (high-order)

0x18

R

0x00

Interrupt Status Register (low-order)

0x19

R

0x00

Interrupt Status Register (high-order)

Note: *Values shown in hexadecimal format. Type designations: "R" – read-only, "R/W" – read/write, "–" – Not used (to accommodate

16-bit APB access)