数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

COREAI-AR 数据表(PDF) 18 Page - Actel Corporation

部件名 COREAI-AR
功能描述  CoreAI
PDF  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ACTEL [Actel Corporation]
网页  http://www.actel.com
标志 ACTEL - Actel Corporation

COREAI-AR 数据表(HTML) 18 Page - Actel Corporation

Back Button COREAI-AR Datasheet HTML 14Page - Actel Corporation COREAI-AR Datasheet HTML 15Page - Actel Corporation COREAI-AR Datasheet HTML 16Page - Actel Corporation COREAI-AR Datasheet HTML 17Page - Actel Corporation COREAI-AR Datasheet HTML 18Page - Actel Corporation COREAI-AR Datasheet HTML 19Page - Actel Corporation COREAI-AR Datasheet HTML 20Page - Actel Corporation COREAI-AR Datasheet HTML 21Page - Actel Corporation COREAI-AR Datasheet HTML 22Page - Actel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 25 page
background image
CoreAI
18
v2.0
ACM Interface
The ACM interface is used to configure the analog quads
and RTC within the AB macro. Various features of the
analog quads need to be set prior to correct operation of
the ADC, including the pre-scaler circuits in each of the
AV, AC, and AT analog input ports that will be accessed
in the user’s design. The SmartGen software, included
with Libero IDE, can be used to configure the various
pre-scaler settings for each quad, as well as the functions
used (voltage monitor, current monitor, temperature
monitor, gate-driver output driver strengths, etc.).
Consult the Fusion datasheet for details on how each
pre-scaler should be set, relative to the design-specific
voltage, current, or temperature ranges used.
The internal address map of the ACM is shown in
Table 32.
Note that the ACM must operate with a clock frequency
that is less than or equal to 10 MHz; to achieve this
requirement,
the
user
must
set
the
clock-divider
appropriately via the ACM_CLK_DIV parameter/generic.
For example, if the system clock frequency (PCLK) is
50 MHz, ACM_CLK_DIV can be set to 3, which would
generate an ACM clock frequency of 50/(23) = 6.25 MHz.
ACM reads and writes are synchronized to the internally
generated ACM clock. Since the ACM clock is operating
at a lower frequency than the system clock (PCLK) used
by CoreAI, various status and interrupt status registers
have been implemented to indicate when ACM read and
write accesses are busy or completed (see Table 10 on
page 12 and Table 30 on page 17).
Table 32 • ACM Address Map (Analog Quads and RTC)*
PADDR[4:0]
Name
Description
Associated Peripheral
0x00
Reserved
Unused
Analog Quad 0
0x01
AQ0
Byte 0 (AV0 control)
Analog Quad
0x02
AQ0
Byte 1 (AC0 control)
Analog Quad
0x03
AQ0
Byte 2 (AG0 control)
Analog Quad
0x04
AQ0
Byte 3 (AT0 control)
Analog Quad
Analog Quad 1
0x05
AQ1
Byte 0 (AV1 control)
Analog Quad
0x06
AQ1
Byte 1 (AC1 control)
Analog Quad
0x07
AQ1
Byte 2 (AG1 control)
Analog Quad
0x08
AQ1
Byte 3 (AT1 control)
Analog Quad
Analog Quad
Analog Quad 9
0x25
AQ9
Byte 0 (AV9 control)
Analog Quad
0x26
AQ9
Byte 2 (AC9 control)
Analog Quad
0x27
AQ9
Byte 2 (AG9 control)
Analog Quad
0x28
AQ9
Byte 3 (AT9 control)
Analog Quad
0x29
Reserved
Unused
0x30
Reserved
Unused
Unused
0x3E
Reserved
Unused
Note: *Address values are given in hexadecimal format.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com