CoreAI

16

v2.0

Table 27 • Read FIFO Status Register

Bits

Name

Function

7:4

Reserved

Not used

3

AEMPTY

Read FIFO Almost Empty

1 – The read FIFO is almost empty (based on the value of the USE_RDFIFO_AEVAL parameter/

generic).

0 – The read FIFO is not almost empty.

2

EMPTY

Read FIFO Empty

1 – The read FIFO is empty.

0 – The read FIFO is not empty.

1

AFULL

Read FIFO Almost Full

1 – The read FIFO is almost full (based on the value of the USE_RDFIFO_AFVAL parameter/generic).

0 – The read FIFO is not almost full.

0

FULL

Read FIFO Full

1 – The read FIFO is full.

0 – The read FIFO is not full.

Table 28 • Interrupt Enable Register (low-order)

Bits

Name

Function

7

Reserved

Not used

6:0

INTEN[6:0]

Low-Order Interrupt Enables

Each of these bits is ANDed with each of the bits in the INT[6:0] register to contribute to the ORed

INTERRUPT output. To mask the contribution of the corresponding bit in the INT[6:0] register, set

that bit to 0; to enable the contribution, set that bit to 1. Note that the INTEN[6:0] bits only mask

what appears on the INTERRUPT output and that the INT[6:0] register bits will always be active to

reflect current interrupt source conditions.

Table 29 • Interrupt Enable Register (high-order)

Bits

Name

Function

7:0

INTEN[14:7]

High-Order Interrupt Enables

Each of these bits is ANDed with each of the bits in the INT[14:7] register to contribute to the ORed

INTERRUPT output. To mask the contribution of the corresponding bit in the INT[14:7] register, set

that bit to 0; to enable the contribution, set that bit to 1. Note that the INTEN[14:7] bits only mask

what appears on the INTERRUPT output and that the INT[14:7] register bits will always be active to

reflect current interrupt source conditions.