COREAI-AR datasheet(23/25 Pages) ACTEL

23 / 25 page

CoreAI

v2.0

ADC Result Read FIFO

An optional read FIFO, capable of holding up to 256

analog-to-digital conversions, is instantiated in CoreAI

when the USE_RDFIFO parameter/generic is set to 1. The

controlling element that is connected to CoreAI (internal

or external microprocessor or microcontroller, or custom

FPGA logic) can read resulting ADC conversions from this

FIFO when desired. Resulting ADC conversion data is

always written into the FIFO 12 bits at once, regardless of

the ADC resolution (8-, 10-, or 12-bit), and is MSB-

justified so that the resulting values are always of the

same order of magnitude. The steps for reading resulting

ADC conversion data from the read FIFO are as follows:

1. Read the Read FIFO Status register to check if

there is data in the FIFO (not empty).

2. If the APB_16BIT_DATA parameter/generic is set to

0 (8-bit mode), read the Read FIFO Data Output

then the upper 4 bits of ADC conversion data. If

the APB_16BIT_DATA parameter/generic is set to 1

(16-bit mode), read the Read FIFO Data Output

conversion data.

3. Repeat steps 1 and 2 until the Read FIFO is empty.

Note that although the ADC conversion results are

stored as one 16-bit word, the four upper bits of this 16-

bit word are reserved for possible future use. Since there

is no channel information associated with each ADC

conversion word, it is up to the user to maintain

temporal coherency between conversions and resulting

data.

Interrupt Logic

Although polling operations have been described to

control the ACM and ADC, wherein status registers are

periodically read (polled), the INTERRUPT output may be

connected to a microprocessor or microcontroller to

indicate similar events (e.g., ACM reads and writes

completing, ADC calibration events, read FIFO events,

etc.). In this case, interrupt service routines may be

written in software to determine what actions, if any,

should be taken for each of the interrupt events. Any or

all interrupt events can be disabled by writing logic 0

values to the INTEN[14:0] register bits to mask the effect

of each of the interrupt sources; it is the responsibility of

the microprocessor/microcontroller software developer

to determine what should or should not be masked.

Note: 8-bit APB reads and writes are shown.

Figure 8 • ADC End of Conversion

PCLK

PADDR[4:0]

PWRITE

PSEL

PENABLE

PWDATA[7:0]

PRDATA[7:0]

ADCStat(hi)

ADCStat(lo)

ADC Conversion Ends

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