v1.4

1

I/O Structures in IGLOOe and ProASIC3E Devices

Introduction

Low-power flash devices feature a flexible I/O structure, supporting a range of mixed voltages (1.2 V,

ProASIC3E families support Pro I/Os.

Users designing I/O solutions are faced with a number of implementation decisions and

configuration choices that can directly impact the efficiency and effectiveness of their final design.

The flexible I/O structure, supporting a wide variety of voltages and I/O standards, enables users to

Design Environment (IDE) provides an easy way to implement I/O that will result in robust I/O

design.

This document first describes the two different I/O types in terms of the standards and features

they support. It then explains the individual features and how to implement them in Actel's Libero

IDE.

Figure 1 • I/O Block Logical Representation

Input

Register

E = Enable Pin

A

Y

PAD

1

2

3

4

5

6

OCE

ICE

ICE

Input

Register

Input

Register

CLR/PRE

CLR/PRE

CLR/PRE

CLR/PRE

CLR/PRE

Pull-Up/-Down

Resistor Control

Signal Drive Strength

and Slew Rate Control

Output

Register

Output

Register

To FPGA Core

From FPGA Core

Output

Enable

Register

OCE

I/O / CLR or I/O / PRE / OCE

I/O / Q0

I/O / Q1

I/O / ICLK

I/O / D0

I/O / D1 / ICE

I/O / OCLK

I/O / OE

Scan

Scan

Scan