I/O Structures in IGLOOe and Pro ASIC3E Devices

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GTL 2.5 V (Gunning Transceiver Logic 2.5 V)

This is a low-power standard (JESD 8-3) for electrical signals used in CMOS circuits that allows for

low electromagnetic interference at high transfer speeds. It has a voltage swing between 0.4 V and

GTL 3.3 V (Gunning Transceiver Logic 3.3 V)

GTL+ (Gunning Transceiver Logic Plus)

This is an enhanced version of GTL that has defined slew rates and higher voltage levels. It requires

a differential amplifier input buffer and an open-drain output buffer. Even though the output is

Differential Standards

These standards require two I/Os per signal (called a “signal pair”). Logic values are determined by

the potential difference between the lines, not with respect to ground. This is why differential

drivers and receivers have much better noise immunity than single-ended standards. The

differential interface standards offer higher performance and lower power consumption than their

single-ended counterparts. Two I/O pins are used for each data transfer channel. Both differential

standards require resistor termination.

LVPECL (Low-Voltage Positive Emitter Coupled Logic)

LVPECL requires that one data bit be carried through two signal lines; therefore, two pins are

needed per input or output. It also requires external resistor termination. The voltage swing

between the two signal lines is approximately 850 mV. When the power supply is +3.3 V, it is

commonly referred to as Low-Voltage PECL (LVPECL). Refer to the device datasheet for the full

implementation of the LVPECL transmitter and receiver.

LVDS (Low-Voltage Differential Signal)

LVDS is a moderate-speed differential signaling system, in which the transmitter generates two

different voltages that are compared at the receiver. LVDS uses a differential driver connected to a

terminated receiver through a constant-impedance transmission line. It requires that one data bit

be carried through two signal lines; therefore, the user will need two pins per input or output. It

also requires external resistor termination. The voltage swing between the two signal lines is

a high-speed LVDS standard that has its own user specification. Refer to the device datasheet for

the full implementation of the LVDS transmitter and receiver.

Figure 8 • Differential Topology

DEVICE 1

GND

OUTn

OUTp

INn

INp

DEVICE 2

GND