I/O Structures in IGLOOe and Pro ASIC3E Devices

v1.4

37

Part Number and Revision Date

This document contains content extracted from the Device Architecture section of the datasheet,

combined with content previously published as an application note describing features and

functions of the device. To improve usability for customers, the device architecture information has

now been combined with usage information, to reduce duplication and possible inconsistencies in

published information. No technical changes were made to the datasheet content unless explicitly

listed. Changes to the application note content were made only to be consistent with existing

datasheet information.

Part Number 51700094-024-3

Revised December 2008

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version

Changes in Current Version (v1.4)

Page

v1.3

(October 2008)

The terminology in the "Low-Power Flash Device I/O Support" section was

revised.

2

v1.2

(June 2008)

The "Low-Power Flash Device I/O Support" section was revised to include new

families and make the information more concise.

2

v1.1

(March 2008)

The following changes were made to the family descriptions in Table1·Flash-

Based FPGAs:

•

ProASIC3L was updated to include 1.5 V.

•

The number of PLLs for ProASIC3E was changed from five to six.

2

v1.0

(January 2008)

This document was previously part of I/O Structures in IGLOO and ProASIC3

Devices. To provide information specific to IGLOOe, ProASIC3E, and

ProASIC3EL, the content was separated and made into a new document.

For information on other low-power flash family I/O structures, refer to the

following documents:

I/O Structures in IGLOO and ProASIC3 Devices contains information specific to

IGLOO, ProASIC3, and ProASIC3L I/O features.

I/O Structures in IGLOO PLUS Devices contains information specific to IGLOO

PLUS I/O features.

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