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PROASIC3E 数据表(PDF) 34 Page - Actel Corporation |
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PROASIC3E 数据表(HTML) 34 Page - Actel Corporation |
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34 / 37 page ![]() I/O Structures in IGLOOe and ProASIC3E Devices 34 v1.4 Board-Level Considerations Low-power flash devices have robust I/O features that can help in reducing board-level components. The devices offer single-chip solutions, which makes the board layout simpler and more immune to signal integrity issues. Although, in many cases, these devices resolve board-level issues, special attention should always be given to overall signal integrity. This section covers important board-level considerations to facilitate optimum device performance. Termination Proper termination of all signals is essential for good signal quality. Nonterminated signals, especially clock signals, can cause malfunctioning of the device. For general termination guidelines, refer to the Board-Level Considerations application note for Actel FPGAs. Also refer to Pin Descriptions for termination requirements for specific pins. Low-power flash I/Os are equipped with on-chip pull-up/-down resistors. The user can enable these resistors by instantiating them either in the top level of the design (refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide for the available I/O macros with pull-up/-down) or in the I/O Attribute Editor in Designer if generic input or output buffers are instantiated in the top level. Unused I/O pins are configured as inputs with pull-up resistors. As mentioned earlier, low-power flash devices have multiple programmable drive strengths, and the user can eliminate unwanted overshoot and undershoot by adjusting the drive strengths. Figure 20 • User I/O Naming Conventions of IGLOOe and ProASIC3E Devices – Top View GNDQ VMV7 VMV6 GNDQ V CC V CC V COMPLF V CCPLF V COMPLE V CCPLE V COMPLA V CCPLA GND V CCIB7 V CCIB6 GND V CC GNDQ VMV2 GND TRST TDO VMV3 GNDQ V COMPLB V COMPLC V CCPLB V CCPLC V JTAG V CC V CC V COMPLD V PUMP V CCPLD V CCIB2 GND V CC V CCIB3 CCC/PLL “D” Bank 5 Bank 4 JTAG AGLE600/A3PE600 A3PE1500 AGLE3000A3PE3000 Bank 0 Bank 1 CCC/PLL “C” CCC/PLL “B” CCC/PLL “E” CCC/PLL “F” CCC/PLL “A” |
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