I/O Structures in IGLOOe and Pro ASIC3E Devices

v1.4

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Solution 2

The board-level design must ensure that the reflected waveform at the pad does not exceed the

voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure

long-term reliability.

This scheme will also work for a 3.3 V PCI/PCI-X configuration, but the internal diode should not be

used for clamping, and the voltage must be limited by the external resistors and Zener, as shown in

Figure 11. Relying on the diode clamping would create an excessive pad DC voltage of

3.3V+0.7 V=4V.

Figure 10 • Solution 1

Figure 11 • Solution 2

Solution 1

5.5 V

3.3 V

Requires two board resistors,

LVCMOS 3.3 V I/Os

I/O Input

Rext1

Rext2

Solution 2

5.5 V

3.3 V

Requires one board resistor, one

Zener 3.3 V diode, LVCMOS 3.3 V I/Os

I/O Input

Rext1

Zener

3.3 V