CDK8307 datasheet(8/29 Pages) CADEKA

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PRELIMINARY Data Sheet

Pin Assignments

(Continued)

Pin No.

Pin Name

Description

Power-down input

LCKP

LVDS bit clock, positive output

LCKN

LVDS bit clock, negative output

D1P

LVDS channel 1, positive output

D1N

LVDS channel 1, negative output

D2P

LVDS channel 2, positive output

D2N

LVDS channel 2, negative output

D3P

LVDS channel 3, positive output

D3N

LVDS channel 3, negative output

D4P

LVDS channel 4, positive output

D4N

LVDS channel 4, negative output

D5P

LVDS channel 5, positive output

D5N

LVDS channel 5, negative output

D6P

LVDS channel 6, positive output

D6N

LVDS channel 6, negative output

D7P

LVDS channel 7, positive output

D7N

LVDS channel 7, negative output

D8P

LVDS channel 8, positive output

D8N

LVDS channel 8, negative output

FCLKP

LVDS frame clock (1x), positive output

FCLKN

LVDS frame clock (1x), negative output

RESETN

Reset SPI interface

62, 64, 66, 67, 69

Not connected

VCM

Common mode output pin, 0.5 AVDD

CLKP

Positive differential input clock

CLKN

Negative differential input clock.

OVDD

Digital CMOS inputs supply voltage (1.7V to 3.6V)

CSN

Chip select enable. Active low.

SDATA

Serial data input

SCLK

Serial clock input

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