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CDK8307 数据表(PDF) 12 Page - Cadeka Microcircuits LLC.

部件名 CDK8307
功能描述  12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS
PDF  29 Pages
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制造商  CADEKA [Cadeka Microcircuits LLC.]
网页  http://www.cadeka.com
标志 CADEKA - Cadeka Microcircuits LLC.

CDK8307 数据表(HTML) 12 Page - Cadeka Microcircuits LLC.

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©2009 CADEKA Microcircuits LLC
www.cadeka.com
12
PRELIMINARY Data Sheet
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Sleep Channel Mode Dissipation
Power dissipation with all chs in sleep mode
80
mW
Sleep Channel Mode Savings
Power dissipation savings per channel off
28
mW
Clock Inputs
Maximum Conversion Rate
50
MSPS
Minimum Conversion Rate
20
MSPS
Electrical Characteristics - CDK8307D
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
SNR
Signal to Noise Ratio
FIN = 8MHz
72.2
dBFS
SINAD
Signal to Noise and Distortion Ratio
FIN = 8MHz
71.5
dBFS
SFDR
Spurious Free Dynamic Range
FIN = 8MHz
82
dBc
HD2
Second order Harmonic Distortion
FIN = 8MHz
95
dBc
HD3
Third order Harmonic Distortion
FIN = 8MHz
82
dBc
ENOB
Effective number of Bits
11.6
bits
Crosstalk
Signal applied to 7 chs (FIN0). Measurement
taken on one ch, full scale at FIN1. FIN1 =
8MHz, FIN0 = 9.9MHz
95
dBc
Power Supply
Analog supply current
145
mA
Digital supply current
Digital and output driver supply
67
mA
Analog power Dissipation
261
mW
Digital power Dissipation
121
mW
Total power Dissipation
382
mW
Power Down Dissipation
10
μW
Sleep Mode Dissipation
96
mW
Sleep Channel Mode Dissipation
Power dissipation with all chs in sleep mode
98
mW
Sleep Channel Mode Savings
Power dissipation savings per channel off
38
mW
Clock Inputs
Maximum Conversion Rate
65
MSPS
Minimum Conversion Rate
20
MSPS
Electrical Characteristics - CDK8307C Continued



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