数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

CDK8307 数据表(PDF) 15 Page - Cadeka Microcircuits LLC.

部件名 CDK8307
功能描述  12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS
PDF  29 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CADEKA [Cadeka Microcircuits LLC.]
网页  http://www.cadeka.com
标志 CADEKA - Cadeka Microcircuits LLC.

CDK8307 数据表(HTML) 15 Page - Cadeka Microcircuits LLC.

Back Button CDK8307 Datasheet HTML 11Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 12Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 13Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 14Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 15Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 16Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 17Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 18Page - Cadeka Microcircuits LLC. CDK8307 Datasheet HTML 19Page - Cadeka Microcircuits LLC. Next Button
Zoom Inzoom in Zoom Outzoom out
 15 / 29 page
background image
©2009 CADEKA Microcircuits LLC
www.cadeka.com
15
PRELIMINARY Data Sheet
Serial Interface
The CDK8307 configuration registers can be accessed through a serial interface formed by the pins SDATA (serial
interface data), SCLK (serial interface clock) and CSN (chip select, active low). The following occurs when CSN is set low:
n
Serial data are shifted into the chip
n
At every rising edge of SCLK, the value present at SDATA is latched
n
SDATA is loaded into the register every 24th rising edge of SCLK
Multiples of 24-bit words data can be loaded within a single active CSN pulse. If more than 24 bits are loaded into
SDATA during one active CSN pulse, only the first 24 bits are kept. The excess bits are ignored. Every 24-bit word is
divided into two parts:
n
The first eight bits form the register address
n
The remaining 16 bits form the register data
Acceptable SCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled.
Timing Diagram
Figure 5 shows the timing of the serial port interface. Table 1 below explains the timing variables used in the Timing
Diagram.
CSN
A7
tcs
tlo
th
thi
tclk
ts
tch
tch
i
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDATA
Figure 5. Serial Port Interface Timing Diagram
Table 1. Serial Port Interface Timing Definitions
Parameter
Description
Minimum Value
Unit
tcs
Setup time between CSN and SCLK
8
ns
tch
Hold time between CSN and SCLK
8
ns
thi
SCLK high time
20
ns
tlo
SCLK low time
20
ns
tclk
SCLK period
50
ns
ts
Data setup time
5
ns
th
Data hold time
5
ns
Register Initialization
Before CDK8307 can be used, the internal registers must be initialized to their default values. This can be done
immediately after applying supply voltage to the circuit. Initialization can be done in one of two ways:
1. By applying a low-going pulse on the RESET pin
2. By using the serial interface to set the RST bit high. Internal registers are reset to default values when this
bit is set. The RST bit is self-reset to zero. When using this method, do not apply any low-going pulse on the
RESETN pin.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com