©2009 CADEKA Microcircuits LLC

www.cadeka.com

23

PRELIMINARY Data Sheet

Table 15. Full Scale Control

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

fs_cntrl<5:0>

Fine adjust ADC full scale range

0% change

X X X X X X

55

The full-scale voltage range of CDK8307 can be adjusted using an internal 6-bit DAC controlled by the

fs_cntrl register.

Changing the value in the register by one step, adjusts the full-scale range approximately 0.3%. This leads to a maximum

range of ±10% adjustment. Table 16 shows how the register settings correspond to the full-scale range. Note that the

values for full-scale range adjustment are approximate. The DAC is, however, guaranteed to be monotonous.

The full-scale control and the programmable gain features differ in two major ways:

1. The full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable

gain is a digital feature.

2. The programmable gain feature has much coarser gain steps and larger range than the full-scale control.

Table 16. Register Values with Corresponding Change in Full-Scale Range

fs_cntrl <5:0>

Full-Scale Range Adjustment

111111

+9.7%

...

...

100001

+0.3%

100000

+0%

011111

-0.3%

...

...

000000

-10%

Table 17. Clock Frequency

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

clk_freq<1:0>

Input clock frequency

65MHz

X X

56

To optimize startup time a register is provided where the input clock frequency can be set. Some internal circuitry has

startup times that are frequency independent. Default counter values are set to accommodate these startup times at

the maximum clock frequency. This will lead to increased startup times at low clock frequency. Setting the value of this

register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual

startup time, such that the startup time will be reduced.

Table 18. Clock Frequency Settings

clk_freq <1:0>

Clock Frequency (MHz)

00

65

01

45

10

30

11

20