©2009 CADEKA Microcircuits LLC

www.cadeka.com

17

PRELIMINARY Data Sheet

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

phase_ddr<1:0> Controls the phase of LCLK

output relative to data

90 degrees

X X

42

pat_deskew

Enable deskew pattern mode

Inactive

0 X

45

pat_sync

Enable sync pattern mode

Inactive

X 0

btc_mode

Binary two's complement

format for ADC output data

Straight

offset binary

X

46

msb_first

Serialized ADC output data

comes out with MSB first

LSB-first

output

X

en_sdr

Enable SDR output mode. LCLK

becomes a 12x input clock

DDR

output mode

X

fall_sdr

Controls whether the LCLK ris-

ing or falling edge comes in the

middle of the data window when

operating in SDR mode

Rising edge

of LCLK

comes in the

middle of the

data window

X

1

perfm_cntrl

ADC performance control

Nominal

X X X

50

ext_vcm_bc

VCM buffer driving strength

control

Nominal

X X

lvds_pd_mode

Controls LVDS power down

mode

High z mode

X

52

lvds_num_bits

Sets the number of LVDS

output bits

13-bit

X 0

53

fs_cntrl

Fine adjust ADC full scale range

0% change

X X X X X X

55

clk_freq

Input clock frequency

65MHz

X X

56

Description of Serial Registers

Table 3. Software Reset

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

rst

Self-clearing software reset

Inactive

X

00

Setting the

rst register bit to '1', resets all internal registers including the rst register bit itself.

Table 4. Power-Down Modes

Name

Description

Default

D

1

5

D

1

4

D

1

3

D

1

2

D

1

1

D

1

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address

In Hex

pd_ch<8:1>

Channel-specific power-down

Inactive

X X X X X X X X

0F

sleep

Go to sleep-mode

Inactive

X

pd

Go to power-down

Inactive

X

pd_pin_cfg

Configures the PD pin for

sleep-mode

PD pin con-

figured for

power-down

mode.

X

lvds_pd_mode

Controls LVDS power down

mode

High z mode

X

52

Table 2. Summary of Functions Supported by the Serial Interface

(Continued)