CY7C68053
Document # 001-06120 Rev *I
Page 16 of 40
5. Register Summary
FX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in greater detail.
Table 8. FX2LP18 Register Summary
Hex
Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform
descriptor 0, 1, 2, 3 data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
E480 128 Reserved
GENERAL CONFIGURATION
E50D
GPCR2
General Purpose Configura-
tion Register 2
Reserved
Reserved
Reserved
FULL_SPEED
_ONLY
Reserved
Reserved
Reserved
Reserved
00000000 R
E600
1
CPUCS
CPU Control and Status
0
0
PORTCSTB
CLKSPD1
CLKSPD0
CLKINV
CLKOE
8051RES
00000010 rrbbbbbr
E601
1
IFCONFIG
Interface Configuration
(Ports, GPIF, Slave FIFOs)
IFCLKSRC
3048MHZ
IFCLKOE
IFCLKPOL
ASYNC
GSTATE
IFCFG1
IFCFG0
10000000 RW
E602
1
PINFLAGSAB[10]
Slave FIFO FLAGA and
FLAGB pin configuration
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000 RW
E603
1
PINFLAGSCD[10]
Slave FIFO FLAGC and
FLAGD pin configuration
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000 RW
E604
1
FIFORESET[10]
Restore FIFOs to default
state
NAKALL
0
0
0
EP3
EP2
EP1
EP0
xxxxxxxx W
E605
1
BREAKPT
Breakpoint control
0
0
0
0
BREAK
BPPULSE
BPEN
0
00000000 rrrrbbbr
E606
1
BPADDRH
Breakpoint address H
A15
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx RW
E607
1
BPADDRL
Breakpoint address L
A7
A6
A5
A4
A3
A2
A1
A0
xxxxxxxx RW
E608
1
Reserved
Reserved
0
0
0
0
0
0
0
0
00000000 rrrrrrbb
E609
1
FIFOPINPOLAR[10]
Slave FIFO interface pins
polarity
0
0
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
E60A
1
REVID
Chip revision
rv7
rv6
rv5
rv4
rv3
rv2
rv1
rv0
RevA
00000001
R
E60B
1
REVCTL[10]
Chip revision control
0
0
0
0
0
0
dyn_out
enh_pkt
00000000 rrrrrrbb
UDMA
E60C
1
GPIFHOLDAMOUNT MSTB hold time
(for UDMA)
0
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3
Reserved
ENDPOINT CONFIGURATION
E610
1
EP1OUTCFG
Endpoint 1-OUT
configuration
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E611
1
EP1INCFG
Endpoint 1-IN
configuration
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E612
1
EP2CFG
Endpoint 2 configuration
VALID
DIR
TYPE1
TYPE0
SIZE
0
BUF1
BUF0
10100010 bbbbbrbb
E613
1
EP4CFG
Endpoint 4 configuration
VALID
DIR
TYPE1
TYPE0
0
0
0
0
10100000 bbbbrrrr
E614
1
EP6CFG
Endpoint 6 configuration
VALID
DIR
TYPE1
TYPE0
SIZE
0
BUF1
BUF0
11100010 bbbbbrbb
E615
1
EP8CFG
Endpoint 8 configuration
VALID
DIR
TYPE1
TYPE0
0
0
0
0
11100000 bbbbrrrr
2
Reserved
E618
1
EP2FIFOCFG[10]
Endpoint 2/Slave FIFO
configuration
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E619
1
EP4FIFOCFG[10]
Endpoint 4/Slave FIFO
configuration
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E61A
1
EP6FIFOCFG[10]
Endpoint 6/Slave FIFO
configuration
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E61B
1
EP8FIFOCFG[10]
Endpoint 8/Slave FIFO
configuration
0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN
0
WORDWIDE 00000101 rbbbbbrb
E61C
4
Reserved
E620
1
EP2AUTOINLENH[10 Endpoint 2 AUTOIN
packet length H
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
E621
1
EP2AUTOINLENL[10] Endpoint 2 AUTOIN
packet length L
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E622
1
EP4AUTOINLENH[10
]
Endpoint 4 AUTOIN
packet length H
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
E623
1
EP4AUTOINLENL[10] Endpoint 4 AUTOIN
packet length L
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E624
1
EP6AUTOINLENH[10
]
Endpoint 6 AUTOIN
packet length H
0
0
0
0
0
PL10
PL9
PL8
00000010 rrrrrbbb
E625
1
EP6AUTOINLENL[10] Endpoint 6 AUTOIN
packet length L
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E626
1
EP8AUTOINLENH[10
]
Endpoint 8 AUTOIN
packet length H
0
0
0
0
0
0
PL9
PL8
00000010 rrrrrrbb
E627
1
EP8AUTOINLENL[10] Endpoint 8 AUTOIN
packet length L
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
E628
1
ECCCFG
ECC Configuration
0
0
0
0
0
0
0
ECCM
00000000 rrrrrrrb
E629
1
ECCRESET
ECC Reset
x
x
x
x
x
x
x
x
00000000 W
E62A
1
ECC1B0
ECC1 Byte 0 address
LINE15
LINE14
LINE13
LINE12
LINE11
LINE10
LINE9
LINE8
00000000 R
E62B
1
ECC1B1
ECC1 Byte 1 address
LINE7
LINE6
LINE5
LINE4
LINE3
LINE2
LINE1
LINE0
00000000 R
Note
10. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’
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