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CY7C68053 数据表(PDF) 26 Page - Cypress Semiconductor

部件名 CY7C68053
功能描述  MoBL-USB FX2LP18 USB Microcontroller
PDF  40 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C68053 数据表(HTML) 26 Page - Cypress Semiconductor

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CY7C68053
Document # 001-06120 Rev *I
Page 26 of 40
9.3 Slave FIFO Synchronous Read
IFCLK
SLRD
FLAGS
SLOE
tSRD
tRDH
tOEon
tXFD
tXFLG
DATA
tIFCLK
N+1
tOEoff
N
Figure 9. Slave FIFO Synchronous Read Timing Diagram[16]
Table 12.Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[17]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
ns
tSRD
SLRD to clock setup time
18.7
ns
tRDH
Clock to SLRD hold time
0
ns
tOEon
SLOE turn-on to FIFO data valid
10.5
ns
tOEoff
SLOE turn-off to FIFO data hold
2.15
10.5
ns
tXFLG
Clock to FLAGS output propagation delay
9.5
ns
tXFD
Clock to FIFO data output propagation delay
11
ns
Table 13.Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[17]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
200
ns
tSRD
SLRD to clock setup time
12.7
ns
tRDH
Clock to SLRD hold time
3.7
ns
tOEon
SLOE turn-on to FIFO data valid
10.5
ns
tOEoff
SLOE turn-off to FIFO data hold
2.15
10.5
ns
tXFLG
Clock to FLAGS output propagation delay
13.5
ns
tXFD
Clock to FIFO data output propagation delay
17.31
ns
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