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PI2002 数据表(PDF) 7 Page - Vicor Corporation

部件名 PI2002
功能描述  Active ORing Controller IC with Load Disconnect Feature
PDF  23 Pages
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制造商  VICOR [Vicor Corporation]
网页  http://www.vicorpower.com
标志 VICOR - Vicor Corporation

PI2002 数据表(HTML) 7 Page - Vicor Corporation

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Picor Corporation • picorpower.com
PI2002
Rev1.1 Page 7 of 23
Figure 3: OCT Off time vs. OCT capacitor value
Short Circuit Detect: SCD
This comparator block input (for 10L-TDFN package
only) can be connected to the load directly or
programmed to a higher voltage with a resistor
divider. The SCD function allows the user to define
the (Hard Short) voltage level expected if a non-ideal
short circuit occurs at the load. To prevent damage
of the MOSFETs under this condition (VSCD<335mV)
the gate charge current (IG-SC) is increased by a
factor of approximately 5 times resulting in fast
charging of the MOSFET gates.
This feature
enables the capability to distinguish between a
faulted load versus powering capacitive and low
resistive loads without entering the OCT mode. This
pin can be grounded to provide a fast gate charging
or pulled to VC for lower gate current to drive highly
capacitive loads with resulting slow gate charge
under the fault condition. If the resulting temperature
rise of the MOSFETs is thermally coupled to the
controller, invoking a thermal shutdown, the thermal
time constant of the system will determine the
average duty cycle further protecting the MOSFETs.
The SCD pin is not available in the SO-8 package
version and is internally preset for slow gate charge,
where the Gate source current is 300µA.
VC and Internal Voltage Regulator:
The PI2002 has a separate input (VC) that provides
power to the control circuitry and the gate driver. An
internal regulator clamps the VC voltage to 15.5V.
For high side applications, the VC input should be
high enough above the bus voltage to properly
enhance the external N-channel MOSFETs.
The internal regulator circuit has a comparator to
monitor VC voltage and initiates a FAULT condition
when VC is lower than the VC Under-Voltage
Threshold.
UV:
The Under-Voltage (UV) input trip point can be
programmed through an external resistive divider to
monitor the input voltage.
The UV comparator
initiates a gate low condition turning the MOSFETs
off and initiates a fault condition pulling the
FT pin
low, when UV falls below the Under-Voltage Falling
Threshold.
OV:
The Overvoltage (OV) input trip point (for 10L-TDFN
package only) can be programmed through an
external resistive divider to monitor the input voltage.
The OV comparator initiates a fault condition and
pulls the
FT
pin low when OV rises above the
Overvoltage Rising Threshold. The PI2002 will turn
the Gate output off if the OV and the Forward
Current conditions are both true. The low resistance
redundant paths of an Active ORing system tend to
force all the input sources to the same voltage
making it difficult to identify the noncompliant
source. By ANDing OV with the Forward Current
Threshold the noncompliant source is identified and
disconnected from the system.
The OV pin is not available in the SO-8 package
version and is disabled.
Over-Temperature Detection:
The internal Over-Temperature block monitors the
junction temperature of the controller. The Over-
Temperature threshold is set to 145
°C with -10°C of
hysteresis.
When the controller temperature
exceeds this threshold, the Over-Temperature circuit
pulls GATE pin low and initiates a fault condition and
pulls the FT pin low. By maintaining proper thermal
matching between the controller and the power
MOSFETs, this function can be used to protect the
MOSFETs from thermal runaway conditions.
Gate Driver:
The gate driver (GATE) output is configured to drive
external N-channel MOSFETs. In the high state, the
gate driver applies a current source that is
dependent on the SCD pin voltage. The controller
regulates the gate voltage to 10V above the SN pin
when the VC voltage is 10.5V higher than the SN
pin. Otherwise the gate voltage (VG) to VSN will be
{VG-SN = VC - VSN – 0.5V}. Note that VC is the
controller internal regulated voltage.
When a reverse current fault is initiated, the gate
driver pulls the GATE pin low and discharges the
FET gate with 4A peak capability.



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