PI2002 datasheet(20/23 Pages) VICOR

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PI2002

Rev1.1 Page 20 of 23

Layout Recommendation:

Use the following general guidelines when designing

printed circuit boards. An example of the typical

land pattern for a TDFN PI2002 and SO-8/PowerPak

MOSFET is shown in Figure 23:

•

It is best to connect the gate of the MOSFETs to

the GATE pin of the controller with a short and

wide trace.

•

The GND pin of the controller carries high peak

current and it should be returned to the ground

plane through a low impedance path.

•

Connections from the SP and SN pins to Vin

and Vout respectively very close to the

MOSFETs, SP to Q1 drain pin and SN to Q2

drain pin.

•

The VC bypass capacitor should be located as

close as possible to the VC and GND pins.

Place the PI2002 and VC bypass capacitor on

the same layer of the board. The VC pin and

CVC PCB trace should not contain any vias.

•

Connect all MOSFET Q1 Drain pins together

with a wide trace to reduce trace parasitics and

accommodate

the

high

current

input.

Similarly, connect all MOSFET Q2 Drain pins

together with a wide trace to accommodate the

high current output. Q1 and Q2 Sources should

be very close from each other and their pins

should be connected with a short trace.

•

Connect the power source very close to the Q1

drain connection to reduce the effects of stray

parasitics. If a short trace is not possible,

connect C3 (typically 1µF) as shown in Figure

23.

Figure 23: PI2002 and MOSFET layout

recommendation

Figure 24: PI2002 Mounted on PI2002-EVAL1

Please visit www.picorpower.com for information on PI2002-EVAL1

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