PI2002 datasheet(15/23 Pages) VICOR

15 / 23 page

Picor Corporation • picorpower.com

PI2002

Rev1.1 Page 15 of 23

The MOSFET current rating and maximum power

dissipation are closely related. Generally the lower the

MOSFET Rds(on), the higher the current capability

and the lower the resultant power dissipation. This

leads to reduced thermal management overhead, but

will ultimately be higher cost compared to higher

Rds(on) parts. It is important to understand the

primary design goal objectives for the application in

order to effectively trade off the performance of one

MOSFET versus another.

Power dissipation in active ORing circuits is derived

from the total source current and the on-state

resistance of the selected MOSFET

MOSFET power dissipation:

)

(

Rds

MOSFET

∗

Where :

: Source Current

Rds(on) : MOSFET on-state resistance

Note:

In the calculation use Rds(on) at maximum MOSFET

temperature because Rds(on)

is temperature

dependent. Refer to the normalized Rds(on) curves in

the

MOSFET

manufacturers

datasheet.

Some

MOSFET Rds(on) values may increase by 50% at

125°C compared to values at 25°C.

The Junction Temperature rise is a function of power

dissipation and thermal resistance.

)

(

Rds

Rth

Trise

MOSFET

∗

Where:

Rth : Junction-to-Ambient thermal resistance

Rds(on) and PI2002 sensing:

The PI2002 senses voltage across the ORing

MOSFETs via the SP and SN pins to determine the

status of the current through the MOSFETs. Refer

Figure 1a. When the MOSFETs are fully enhanced,

the total drop across the back to back MOSFETs (and

between SP and SN) is; VSD=Rds(on)*Is * 2.

The reverse current threshold is set for -6mV and

when the differential voltage between the SP & SN

pins is more negative than -6mV, i.e. SP-SN

≤-6mV,

the PI2002 detects a reverse current fault condition

and pulls the MOSFET gate pin low to turn off the

MOSFET and prevent further reverse current. The

reverse current fault protection disconnects the power

source fault condition from the redundant bus and

allows the system to keep running.

The GATE pin output voltage is clamped to 11V

maximum with respect to the SN pin. The 11V clamp

should be adequate for protecting MOSFETs with

maximum Vgs ratings of ±12V or greater.

OV/UV resistor selection:

The UV and OV comparator inputs are used to

monitor the input voltage and will indicate a fault

condition when this voltage is out of range. The UV

and OV pins can be configured in two different ways,

either with a divider on each pin, or with a three-

resistor divider to the same node, enabling the

elimination

one

resistor.

Under-Voltage

monitored by the UV pin input and Over-Voltage is

monitored with the OV pin input.

Note: The OV pin is not available in the SO-8 package

and OV function is disabled.

The Fault pin (

FT ) will indicate a fault (active low)

when the UV pin is below the threshold or when the

OV pin is above the threshold. The UV and OV

thresholds are 0.50V typical with 25mV hysteresis and

their input current is less than ±1µA. It is important to

consider the maximum current that will flow in the

resistor divider and maximum error due to UV and OV

input current. Set the resistor current to 100µA or

higher to maintain 1% accuracy for UV and OV due to

the bias current.

The three-resistor voltage divider configuration for

both UV and OV to monitor the same voltage node is

shown in Figure 17:

)

(

Figure 17: UV & OV three-resistor divider

configuration.

)

(

Set

Ra value based on system allowable current

)

(

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

•

)

(

)

(

()

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

•

)

(

Where:

)

(

: UV threshold voltage

)

(

: OV threshold voltage

V(UV)

: UV voltage

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