ADIS16220

Preliminary Technical Data

Rev. PrE | Page 8 of 16

THEORY OF OPERATION

The ADIS16220 is a wide-bandwidth, digital acceleration sensor

for vibration analysis applications. This sensing system collects

data autonomously and makes it available to any processor

system that supports a 4-wire serial peripheral interface (SPI).

SENSING ELEMENT

Digital vibration sensing in the ADIS16220 starts with a wide-

bandwidth MEMS accelerometer core that provides a linear

motion-to-electrical transducer function. Figure 6 provides a

basic physical diagram of the sensing element and its response

to linear acceleration. It uses a fixed frame and a moving frame

to form a differential capacitance network that responds to

linear acceleration. Tiny springs tether the moving frame to the

fixed frame and govern the relationship between acceleration

and physical displacement. A modulation signal on the moving

plate feeds through each capacitive path into the fixed frame

plates and into a demodulation circuit, which produces the

electrical signal that is proportional to the acceleration acting on

the device.

MOVABLE

FRAME

UNIT

FORCING

CELL

UNIT SENSING

CELL

MOVING

PLATE

FIXED

PLATES

PLATE

CAPACITORS

ANCHOR

ANCHOR

Figure 6. MEMS Sensor Diagram

DATA SAMPLING AND PROCESSING

The ADIS16220 runs autonomously, based on the configuration

in the user control registers. The analog acceleration signal

feeds into an analog-to-digital (ADC) converter stage, which

passes digitized data into the controller for data processing and

capture. Processing options include offset adjustment, filtering,

and checking for preset alarm conditions.

MEMS

SENSOR

CLOCK

CONTROLLER

CAPTURE

BUFFER

CONTROL

REGISTERS

OUTPUT

REGISTERS

TEMP

SENSOR

AIN

SIGNALS

ADC

Figure 7. Simplified Sensor Signal Processing Diagram

USER INTERFACE

SPI Interface

Data collection and configuration commands both use the SPI,

which consists of four wires. The chip select (CS) signal activates

the SPI interface and the serial clock (SCLK) synchronizes the

serial data lines. The serial input data clocks into DIN on the

SCLK rising edge, and the serial output data clocks out of the

DOUT on the SCLK falling edge. Many digital processor

platforms support this interface with dedicated serial ports and

simple instruction sets.

User Registers

The user registers provide addressing for all input/output opera-

tions on the SPI interface. Each 16-bit register has its own unique

bit assignment and has two addresses: one for its upper byte and

one for its lower byte. Table 8 provides a memory map for each

register, along with their function. The control registers use a

dual memory structure. The SRAM controls operation while

the part is on, and facilitates all user configuration inputs. The

flash memory provides nonvolatile storage for control registers

that have flash backup (see Table 8). Storing configuration data

in the flash memory requires a separate command (GLOB_

CMD[12] = 1, DIN = 0xBF10). When the device powers on or

resets, the flash memory contents load into the SRAM, and then

the device starts producing data according to the configuration

in the control registers.

NONVOLATILE

FLASH MEMORY

(NO SPI ACCESS)

MANUAL

FLASH

BACKUP

START-UP

RESET

VOLATILE

SRAM

SPI ACCESS

Figure 8. SRAM and Flash Memory Diagram