Preliminary Technical Data

ADIS16220

Rev. PrE | Page 9 of 16

BASIC OPERATION

The ADIS16220 requires only power, ground, and the four SPI

signals to produce data and make it available to a processor.

Figure 9 provides a schematic for connecting to a SPI-compatible

processor, and includes the two configurable digital I/O lines.

DIO1’s factory default configuration is a busy indicator that

goes high when the devices is capturing data and goes low when

finished.

CS

ADIS16220

SPI SLAVE

SCLK

DIN

DOUT

DIO1

DIO2

SS

VDD

SYSTEM PROCESSOR

SPI MASTER

SCLK

MOSI

MISO

IRQ1

IRQ2

6

5

2

3

1

4

13

16

Figure 9. Electrical Hook-Up Diagram

Table 6. Generic Master Processor Pin Names and Functions

Pin Name

Function

SS

Slave select

IRQ1, IRQ2

Interrupt request inputs

MOSI

Master output, slave input

MISO

Master input, slave output

SCLK

Serial clock

The ADIS16220 SPI interface supports full duplex serial

communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 13. Processor platforms

typically support SPI communication with general-purpose

serial ports that require some configuration in their control

registers. Table 7 provides a list of the most common settings

that require attention to initialize a processor’s serial port for

communication with the ADIS16220.

Table 7. Generic Master Processor SPI Settings

Processor Setting

Description

Master

ADIS16220 operates as a slave

SCLK Rate ≤ 2.25 MHz

Bit rate setting

SPI Mode 3 (1, 1)

Clock polarity/phase (CPOL = 1, CPHA = 1)

MSB-First

Bit sequence

16-Bit

Shift register/data length

User registers govern all data collection and configuration.

Table 8 provides a memory map that includes all user registers,

with references to bit assignment tables that follow the generic

assignments in Figure 10.

UPPER BYTE

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LOWER BYTE

Figure 10. Generic Register Bit Definitions

SPI WRITE COMMANDS

Master processors write to the control registers, one byte at a

time, using the bit assignments in Figure 13. Some configura-

tions require writing both bytes to a register, which takes two

separate 16-bit sequences, whereas others require only one byte.

The programmable registers in Table 8 provide controls for

optimizing sensor operation and for starting various automated

functions. For example, set GLOB_CMD[11] = 1 by writing

0xBF08 to the master processor’s SPI transmit register, which

feeds the DIN line, to start a manual capture sequence. The

manual capture starts immediately after the last bit clocks into

CS

DIN

SCLK

Figure 11. SPI Sequence for Manual Capture Start (DIN = 0xBF08)

SPI READ COMMANDS

Reading data through the SPI requires two consecutive 16-bit

sequences. The first sequence transmits the read command and

address on DIN, and the second receives the resulting data from

DOUT. The 7-bit register address (A6:A0) can represent either

the upper or lower byte address for the target register. For example,

DIN can be either 0x0A00 or 0x0B00 when reading the

CAPT_SUPPLY register.

Figure 12 provides a full-duplex mode example of reading the

CAPT_SUPPLY register. Also, the second SPI segment sets the

device up to read CAPT_TEMP on the following SPI segment

(not shown).

CS

DIN

SCLK

DIN = 0x0A00 PRODUCES CAPT_SUPPLY CONTENTS ON

DOUT DURING THE NEXT SPI SEGMENT

DOUT

SPI SEGMENT 1

SPI SEGMENT 2

0

00010101

0001111

DOUT = 0x0A8F, CAPT_SUPPLY = +3.3V

Figure 12. Example SPI Read Sequence