STM32F107VB datasheet(53/95 Pages) STMICROELECTRONICS

53 / 95 page

STM32F105xx, STM32F107xx

Electrical characteristics

Doc ID 15274 Rev 4

53/95

5.3.12

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 35 are derived from tests

performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL

compliant.

All I/Os are CMOS and TTL compliant (no software configuration required), their

characteristics consider the most strict CMOS-technology or TTL parameters:

For VIH:

–if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included

–if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included

For VIL:

–if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included

–if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included

Table 35.

I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

TTL ports

–0.5

0.8

VIH

Standard IO input high level voltage

VDD+0.5

IO FT(1) input high level voltage

5.5V

VIL

Input low level voltage

CMOS ports

–0.5

0.35 VDD

VIH

Input high level voltage

0.65 VDD

VDD+0.5

Vhys

Standard IO Schmitt trigger voltage

hysteresis(2)

200

IO FT Schmitt trigger voltage hysteresis(2)

5% VDD

(3)

Ilkg

Input leakage current (4)

VSS VIN VDD

Standard I/Os

‒1

µA

VIN= 5 V, I/O FT

RPU

Weak pull-up equivalent

resistor(5)

All pins except for

PA10

VIN ?"VSS

PA10

RPD

Weak pull-down

equivalent resistor(5)

All pins except for

PA10

VIN ?"VDD

PA10

CIO

I/O pin capacitance

1. FT = Five-volt tolerant.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order)

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