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STM32F107VB 数据表(PDF) 11 Page - STMicroelectronics

部件名 STM32F107VB
功能描述  Connectivity line, ARM-based 32-bit MCU with 64/256 KB Flash, USB OTG, Ethernet, 10 timers, 2 CANs, 2 ADCs, 14 communication interfaces
PDF  95 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F107VB 数据表(HTML) 11 Page - STMicroelectronics

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STM32F105xx, STM32F107xx
Description
Doc ID 15274 Rev 4
11/95
2.2
Full compatibility throughout the family
The STM32F105xx and STM32F107xx constitute the connectivity line family whose
members are fully pin-to-pin, software and feature compatible.
The STM32F105xx and STM32F107xx are a drop-in replacement for the low-density
(STM32F103x4/6), medium-density (STM32F103x8/B) and high-density
(STM32F103xC/D/E) performance line devices, allowing the user to try different memory
densities and peripherals providing a greater degree of freedom during the development
cycle.
Table 3.
STM32F105xx and STM32F107xx family versus STM32F103xx family(1)
STM32
device
Low-density
STM32F103xx devices
Medium-density
STM32F103xx devices
High-density
STM32F103xx devices
STM32F105xx
STM32F107xx
Flash
size (KB)
16
32
32
64
128
256
384
512
64
128
256
128
256
RAM
size (KB)
610
10
20
20
48
64
64
20
32
64
48
64
144 pins
5 × USARTs
4 × 16-bit timers,
2 × basic timers, 3 × SPIs,
2 × I2Ss, 2 × I2Cs, USB,
CAN, 2 × PWM timers
3 × ADCs, 2 × DACs,
1 × SDIO, FSMC (100-
and 144-pin packages(2))
100 pins
3 × USARTs
3 × 16-bit
timers
2 × SPIs,
2 × I2Cs, USB,
CAN,
1 × PWM timer
2 × ADCs
5 × USARTs,
4 × 16-bit timers,
2 × basic timers,
3 × SPIs,
2 × I2Ss,
2 × I2Cs,
USB OTG FS,
2 × CANs,
1 × PWM timer,
2 × ADCs,
2 × DACs
5 × USARTs,
4 × 16-bit timers,
2 × basic timers,
3 × SPIs,
2 × I2S,
1 × I2C,
USB OTG FS,
2 × CANs,
1 × PWM timer,
2 × ADCs,
2 × DACs,
Ethernet
64 pins
2 × USARTs
2 × 16-bit timers
1 × SPI, 1 × I2C, USB,
CAN,
1 × PWM timer
2 × ADCs
2 × USARTs
2 × 16-bit
timers
1 × SPI,
1 × I2C,
USB, CAN,
1 × PWM
timer
2 × ADCs
48 pins
36 pins
1. Please refer to Table 5: Pin definitions for peripheral availability when the I/O pins are shared by the peripherals required
by the application.
2. Ports F and G are not available in devices delivered in 100-pin packages.



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