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STM32F107VB 数据表(PDF) 21 Page - STMicroelectronics |
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STM32F107VB 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 95 page ![]() STM32F105xx, STM32F107xx Description Doc ID 15274 Rev 4 21/95 2.3.24 Remap capability This feature allows the use of a maximum number of peripherals in a given application. Indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. This has the advantage of making board design and port usage much more flexible. For details refer to Table 5: Pin definitions; it shows the list of remappable alternate functions and the pins onto which they can be remapped. See the STM32F10xxx reference manual for software considerations. 2.3.25 ADCs (analog-to-digital converters) Two 12-bit analog-to-digital converters are embedded into STM32F105xx and STM32F107xx connectivity line devices and each ADC shares up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: G Simultaneous sample and hold G Interleaved sample and hold G Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the standard timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.26 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: G two DAC converters: one for each output channel G 8-bit or 12-bit monotonic output G left or right data alignment in 12-bit mode G synchronized update capability G noise-wave generation G triangular-wave generation G dual DAC channel independent or simultaneous conversions G DMA capability for each channel G external triggers for conversion G input voltage reference VREF+ |
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