MAXQ3183-RAN+ datasheet(35/102 Pages) MAXIM

35 / 102 page

Low-Power, Multifunction, Polyphase AFE

with Harmonics and Tamper Detect

______________________________________________________________________________________

Pulse Configuration—CFQ Output (PLSCFG2) (0x01F)

This register selects which phases are included in the CFQ pulse output and also selects which quantity is accumu-

lated to drive the pulse output.

BIT

NAME

FUNCTION

7:3

QNSEL

CFQ Pulse Output Source Select. This five-bit field determines what meter value is accumulated in

each of the phases to produce the CFQ pulse output. All other values are reserved.

00000 = Net real energy

00001 = Absolute real energy

00010 = Net reactive energy

00011 = Absolute reactive energy

00100 = Apparent energy

00110 = IRMS

00111 = VRMS

01000 = Real energy delivered to load

01001 = Real energy delivered to line

01010 = Reactive energy, quadrant I

01011 = Reactive energy, quadrant II

01100 = Reactive energy, quadrant III

01101 = Reactive energy, quadrant IV

PHASEC

CFQ Phase C Inclusion. When this bit is set, phase C is included in CFQ pulse generation.

PHASEB

CFQ Phase B Inclusion. When this bit is set, phase B is included in CFQ pulse generation.

PHASEA

CFQ Phase A Inclusion. When this bit is set, phase A is included in CFQ pulse generation.

Bit:

Name:

QNSEL

PHASEC

PHASEB

PHASEA

Reset:

0x0

CFP Pulse Width (PLS1_WD) (0x020)

This register designates the width of the CFP pulse, that is, the duration of the period that the CFP pulse is in the

active state. This value is given in ADC frame times (about 360μs). The default value of 0x9C (156 decimal) provides

a pulse width of about 50ms.

Bit:

Name:

CFP Pulse-Width High Byte

Reset:

0x00

Bit:

Name:

CFP Pulse-Width Low Byte

Reset:

0x9C

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