LSM303DLH datasheet(33/47 Pages) STMICROELECTRONICS

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LSM303DLH

Registers description

Doc ID 16941 Rev 1

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The BDU bit is used to inhibit output register updates between the reading of the upper and

lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are

updated continuously. If it is not certain to read faster than output data rate, it is

recommended to set BDU bit to ‘1’. In this way, after the reading of the lower (upper) register

part, the content of that output register is not updated until the upper (lower) part is read

also. This feature avoids reading LSB and MSB related to different samples.

9.1.5

CTRL_REG5_A (24h)

TurnOn bits are used for turning on the sleep-to-wake function.

By setting the TurnOn [1:0] bits to 11, the “sleep-to-wake” function is enabled. When an

interrupt event occurs, the device goes into normal mode, increasing the ODR to the value

defined in CTRL_REG1_A. Although the device is in normal mode, CTRL_REG1_A content

is not automatically changed to “normal mode” configuration.

9.1.6

HP_FILTER_RESET_A (25h)

Dummy register. Reading at this address instantaneously zeroes the content of the internal

high-pass filter. If the high-pass filter is enabled, all three axes are instantaneously set to 0

g. This makes it possible to surmount the settling time of the high-pass filter.

9.1.7

REFERENCE_A (26h)

Table 31.

CTRL_REG5_A register

000

TurnOn1

TurnOn0

Table 32.

CTRL_REG5_A description

TurnOn1,

TurnOn0

Turn-on mode selection for sleep-to-wake function. Default value: 00.

Table 33.

Sleep-to-wake configuration

TurnOn1

TurnOn0

Sleep-to-wake status

Sleep-to-wake function is disabled

Turned on: The device is in low-power mode

(ODR is defined in CTRL_REG1_A)

Table 34.

REFERENCE_A register

Ref7

Ref6

Ref5

Ref4

Ref3

Ref2

Ref1

Ref0

Table 35.

REFERENCE_A description

Ref7 - Ref0

Reference value for high-pass filter. Default value: 00h.

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