LSM303DLH datasheet(43/47 Pages) STMICROELECTRONICS

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LSM303DLH

Registers description

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impacts DRDY and RDY, which cannot be cleared until new data is placed in all the output

registers.

Status register

The status register (SR) is an 8-bit read-only register. This register is used to indicate device

status. SR0 through SR7 indicate bit locations, with

SR denoting the bits that are in the

status register. SR7 denotes the first bit of the data stream.

9.2.8

IR_REG_M (0Ah/0Bh/0Ch)

The identification registers (IR) are used to identify the device. IR0 through IR7 indicate bit

locations, with IRA/IRB/IRC denoting the bits that are in the identification registers A, B & C.

IRA7/IRB7/IRC7 denotes the first bit of the data stream.

The identification value for this device is stored in this register. This is a read-only register.

Table 72.

SR register

000

REN

LOC

RDY

Table 73.

Status register bit designations

MD1

MD0

Mode

SR7 to SR3

These bits must be cleared for correct operation

SR2

REN

Regulator enabled bit. This bit is set when the internal voltage regulator is

enabled. This bit is cleared when the internal regulator is disabled.

SR1

LOCK

Data output register lock. This bit is set when some, but not all, of the six

data output registers have been read. When this bit is set, the six data

output registers are locked and any new data is not placed in these

registers until one of four conditions are met: one, all six have been read or

the mode changed, two, a POR is issued, three, the mode is changed, or

four, the measurement is changed.

SR0

RDY

Ready bit. Set when data is written to all six data registers. Cleared when

the device initiates a write to the data output registers, when in off mode,

and after one or more of the data output registers are written to. When RDY

bit is clear, it shall remain cleared for a minimum of 5 µs. The DRDY pin can

be used as an alternative to the status register for monitoring the device for

conversion data.

Table 74.

IRA_REG_M

100

Table 75.

IRB_REG_M

011

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