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MPC8544EBVTALG 数据表(PDF) 26 Page - Freescale Semiconductor, Inc |
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MPC8544EBVTALG 数据表(HTML) 26 Page - Freescale Semiconductor, Inc |
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26 / 120 page  MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3 26 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 8.3.2 SGMII Transmitter and Receiver DC Electrical Characteristics Table 24 and Table 25 describe the SGMII SerDes transmitter and receiver AC-Coupled DC electrical characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) as depicted in Figure 8. Table 23. SD2_REF_CLK and SD2_REF_CLK AC Requirements Symbol Parameter Description Min Typical Max Units Notes tREF REFCLK cycle time — 10 (8) — ns 1 tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles —— 100 ps — tREFPJ Phase jitter. Deviation in edge location with respect to mean edge location –50 — 50 ps — Note: 1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR. Table 24. DC Transmitter Electrical Characteristics Parameter Symbol Min Typ Max Unit Notes Supply Voltage VDD_SRDS2 0.95 1.0 1.05 V — Output high voltage VOH —— VOS-max + |VOD|–max/2 mV 1 Output low voltage VOL VOS-min –|VOD|-max/2 — — mV Output ringing VRING —— 10 % — Output differential voltage2,3,5 |VOD| 323 500 725 mV Equalization setting: 1.0x 296 459 665 Equalization setting: 1.09x 269 417 604 Equalization setting: 1.2x 243 376 545 Equalization setting: 1.33x 215 333 483 Equalization setting: 1.5x 189 292 424 Equalization setting: 1.71x 162 250 362 Equalization setting: 2.0x Output offset voltage VOS 425 500 577.5 mV 1, 4 Output impedance (single ended) RO 40 — 60 Ω — Mismatch in a pair ΔRO —— 10 % — Change in VOD between 0 and 1 Δ|VOD|— — 25 mV — |
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