MPC8544EBVTALG datasheet(68/120 Pages) FREESCALE

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MPC8544E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50

Ω to

SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it

must be AC-coupled off-chip.

•

The input amplitude requirement

— This requirement is described in detail in the following sections.

Figure 45. Receiver of SerDes Reference Clocks

16.2.2

DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the MPC8544E SerDes reference clock inputs is different depending on the

signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described

below.

•

Differential Mode

— The input amplitude of the differential clock must be between 400 and 1600 mV differential

peak-peak (or between 200 and 800 mV differential peak). In other words, each signal wire of

the differential pair must have a single-ended swing less than 800 mV and greater than 200 mV.

This requirement is the same for both external DC-coupled or AC-coupled connection.

— For external DC-coupled connection, as described in Section 16.2.1, “SerDes Reference

Clock Receiver Characteristics,” the maximum average current requirements sets the

requirement for average voltage (common mode voltage) to be between 100 and 400 mV.

Figure 46 shows the SerDes reference clock input requirement for DC-coupled connection

scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the

clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver

and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above

the command mode voltage (SGND_SRDSn). Figure 47 shows the SerDes reference clock

input requirement for AC-coupled connection scheme.

Input

Amp

n_REF_CLK

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