PCF2129AT datasheet(49/68 Pages) NXP

49 / 68 page

PCF2129A_1

Product data sheet

Rev. 01 — 13 January 2010

49 of 68

NXP Semiconductors

PCF2129A

Integrated RTC, TCXO and quartz crystal

The R/W bit defines the direction of the following single or multiple byte data transfer (read

is logic 1, write is logic 0).

For the format and the timing of the START condition (S), the STOP condition (P), and the

acknowledge bit (A) refer to the I2C-bus specification Ref. 13 “UM10204” and the

characteristics table (Table 55). In the write mode a data transfer is terminated by sending

either a STOP condition or the START condition of the next data transfer.

Table 50.

I2C slave address byte

Slave address

Bit

MSB

LSB

1R/W

Fig 35. Bus protocol, writing to registers

001aaj723

slave address

00h to 1Dh

0 to n

data bytes

write bit

START/

STOP

acknowledge

from PCF2129A

acknowledge

from PCF2129A

acknowledge

from PCF2129A

P/S

Fig 36. Bus protocol, reading from registers

001aaj724

slave address

0 to n data bytes

DATA BYTE

LAST DATA BYTE

read bit

acknowledge

from PCF2129A

acknowledge

from master

no acknowledge

slave address

00h to 1Dh

set register

address

read register

data

write bit

STOP

acknowledge

from PCF2129A

acknowledge

from PCF2129A

PCF2129AT 数据表(PDF) 49 Page - NXP Semiconductors

PCF2129AT 数据表(HTML) 49 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载

链接网址

PCF2129AT 数据表(PDF) 49 Page - NXP Semiconductors

PCF2129AT 数据表(HTML) 49 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表 下载

链接网址

数据表下载