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AS1544 数据表(PDF) 8 Page - ams AG

部件名 AS1544
功能描述  8/4-Channel, 1 Msps, 12-Bit ADC with Sequencer
PDF  29 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1544 数据表(HTML) 8 Page - ams AG

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Revision 1.00
8 - 29
AS1543/44
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Timing Specifications
VDD = 2.7 to 5.25V, VDRIVE
≤ VDD, REFIN = 2.5V; TAMB = -40 to +85°C (unless otherwise specified). Specifications
based on load circuit shown in Figure 3 on page 8.
Figure 3. Load Circuit for Digital Output Timing Specifications
Figure 4. Serial Interface Timing Diagram
Table 4.
Symbol
Min
Typ
Max
Unit
Description
fSCLK
0.01
20
MHz SCLK frequency
tCP
50
ns
SCLK periode
tQUIET
50
ns
Minimum quiet time required between bus relinquish and next
conversion start.
tCSS
10
ns
CSN Fall to SCLK Fall Setup
tCSDOE
20
ns
CSN Fall to DOUT Enabled.
tCSDOV
40
ns
CSN Fall to DOUT Valid.
tCL
0.4 tCP
ns
SCLK Pulse Width Low.
tCH
0.4 tCP
ns
SCLK Pulse Width High.
tDOH
10
ns
SCLK Fall to DOUT Hold.
tDOV
50
ns
SCLK Fall to DOUT Valid.
tDOD
15
50
ns
SCLK Fall to DOUT Disable.
tDS
20
ns
DIN to SCLK Fall Setup.
tDH
5ns
DIN to SCLK Fall Hold.
tCSH
20
ns
Sixteenth SCLK Fall to CSN Rise Hold.
tWAKEUP
1µs
Power-up time from auto shutdown mode.
CLOAD
25pF
DOUT
VDD/2
200µA
IOL
200µA
IOH
2
5
4
3
6
12
14
1
15
16
DB2
DB1
DB0
tCONVERT
DB10
DB11
ADDR0
ADDR1
ADDR2
Tri-State
tDOD
tCH
tDOH
tDOV
tCL
SCLK
CSN
DOUT
DIN
Tri-State
tCSDOE
tDS
tDH
tCSS
tCSH
ADDR3
4 ID Bits
tCSDOV
B
tQUIET
ADDR3
ADDR2
ADDR1
ADDR0
SEQ
WRITE
DC
DC = Don’t Care
DC
DC
DB3
SE/FDN
13



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