www.austriamicrosystems.com

Revision 1.00

23 - 29

AS1543/44

Data Sheet - D e t a i l e d D e s c r i p t i o n

Auto Shutdown (PM1 = 0, PM0 = X)

In this mode, the AS1543/44 automatically enters shutdown after the 14th SLK falling edge of each conversion is

updated. When the device is in shutdown mode, the track/hold circuitry is in hold mode.

Note: The control register maintains its data while in shutdown mode.

Figure 34 shows the operation of the AS1543/44 when it is in automatic shutdown mode The AS1543/44 remains in

shutdown until the next CSN falling edge it receives. On this CSN falling edge, the track and hold that was in hold while

the device was in shutdown will return to track.

Note: Wake-up time from auto shutdown is 1µs.

Figure 34. Auto Shutdown Mode Operation

Notes:

1. Control register data is loaded on the 1st 13 SCLK cycles.

2. Set control register bits PM1 = 1 and PM0 = 1 to keep the device in normal mode.

When running the AS1543/44 with a 20MHz clock, one dummy cycle of 1µs (see Figure 34) (16 SCLKs plus

Track&Hold aquisation time) should be sufficient to ensure the part is fully powered up.

This dummy cycle effectively halves the throughput rate, with every other conversion result being valid. In this mode,

the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion.

Note: The end of shutdown can be controlled by the CSN signal.

Power vs. Throughput Rate

By operating the AS1543/44 in auto shutdown (see page 23) the average power consumption of the ADC decreases at

lower throughput rates. The Power vs. Throughput Rate graph in the Typical Operating Characteristics section shows

how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consump-

tion over time drops accordingly.

If the AS1543/44 is operated in a continuous sampling mode with a throughput rate of 100ksps and a SCLK of 20 MHz

sumption is calculated as follows:

shutdown is one dummy cycle (i.e., 1µs) and the remaining conversion time is another cycle (i.e., 1µs) then the

AS1543/44 will dissipate approximately 18.4mW for 2µs during each conversion cycle. For the remainder of the con-

version cycle (8µs), the device remains in shutdown mode. The AS1543/44 will dissipate approximately 2.5µW for the

remaining 8µs of the conversion cycle. If the throughput rate is 100ksps, the cycle time is 10µs and the average power

dissipated during each cycle is:

((2/10) x 18.4mW) + ((8/10) x 2.5µW) = 3.682mW

(EQ 1)

114 16

DOUT

Data into Control/Shadow Register

Data into Control/Shadow Register

Data into Control/Shadow Register

114 16

114 16

SCLK

DIN

Channel ID Bits + Conversion Results

Invalid Data

Channel ID Bits + Conversion Results

CSN

Device enters automatic

shutdown on 14th SCLK

falling edge as PM1 = 0

Device begins to power

up on falling CSN edge

and remains powered-up

on PM1=1 and PM0=1

Device is fully

powered up

Device enters shutdown

on the 14th SCLK falling

edge as PM1 = 0

Dummy Conversion

Valid Conversion