www.austriamicrosystems.com

Revision 1.00

20 - 29

AS1543/44

Data Sheet - D e t a i l e d D e s c r i p t i o n

Channel Counter Conversion (SEQ = 1, SHADOW = 1)

Figure 30 shows how a sequence of consecutive channels can be converted from without having to program the

shadow register or write to the part on each serial transfer. To exit this mode of operation and revert back to the normal

mode of operation of a multi-channel ADC (as outlined in Figure 29), verify bit WRITE (page 14) = 1 and bits SEQ and

SHADOW = 0 on the next serial transfer.

Figure 30. Bit SEQ = 1, Bit SHADOW = 1 Flowchart

Serial Interface

Figure 31 shows the detailed timing diagram for serial interfacing to the AS1543/44. The serial clock provides the con-

version clock and also controls the transfer of information to and from the AS1543/44 during each conversion.

Figure 31. Serial Interface Timing Diagram

Power On

CSN Falling

Edge

DOUT: Dummy Conversion Result

DIN: Write to Control Register;

Bit WRITE = 1;

Select Coding, Range, SE/FDN,

WEAK/TRIN and Power Mode

Use ADDR3:ADDR0 (see Table 5 on page 14)

for Channel Counter Conversion*

Bit SEQ = 1, Bit SHADOW = 1

Bit WRITE = 1, Bit SEQ = 1, Bit SHADOW = 0

Bit WRITE = 0

DOUT: Conversion Result from pre-

viously selected Channel

Continuously Convert the Selected

Sequence of

Channels and Allow Changes to

Control Register

without Conversion Interruption

DOUT: Conversion Result from previously

selected Channel

Continuously Convert Consecutive

Sequence of

Channels from Channel 0 up to and includ-

ing Previously

Selected ADDR3:ADDR0 in the Control

Register

Bit WRITE = 1,

Bit SEQ = 1,

Bit SHADOW = 0

Bit WRITE = 0

Bit WRITE = 0

Bit WRITE = 1

Bit SEQ = 1

Bit SHADOW = 0

Exit this flow whenever WRITE = 1 and NOT (SEQ = 1, SHADOW = 0)

CSN Falling

Edge

CSN Falling

Edge

*The binary selected channel number

will determine the last channel used for

conversion. e.g.: 0101 = 5 => channel

0:5 will be used for conversion.

2

5

4

3

6

12

14

1

15

16

DB2

DB1

DB0

DB10

DB11

ADDR0

ADDR1

ADDR2

Tri-State

SCLK

CSN

DOUT

DIN

Tri-State

ADDR3

4 ID Bits

B

ADDR3

ADDR2

ADDR1

ADDR0

SEQ

WRITE

DC

DC = Don’t Care

DC

DC

DB3

SE/FDN

13