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AS1544 数据表(PDF) 12 Page - ams AG |
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AS1544 数据表(HTML) 12 Page - ams AG |
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12 / 29 page ![]() www.austriamicrosystems.com Revision 1.00 12 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS1543/44 is a fast, 8/4-channel, 12-bit, single-supply, A/D converter, which can be operated from a 2.7 to 5.25V supply. The AS1543/44 is capable of throughput rates of up to 1Msps when provided with a 20MHz clock. The AS1543/44 features on-chip track/hold, A/D converter, sequencer and a serial interface in a TQFN(4x4)-20 package. The AS1543/44 has 8/4 single-ended or 4/2 fully-differential input channels with a channel sequencer, allowing the selection of the sequence of channels the ADC can cycle through on (each consecutive CSN falling edge). The serial clock input accesses data from the AS1543/44, controls the transfer of data written to the ADC, and provides the clock source for the successive-approximation A/D converter. The analog input range for the AS1543/44 is [0 to VREFIN] or [0V to 2 x VREFIN] for 8/4 single ended input channels or [-VREFIN/2 to +VREFIN/2] or [-VREFIN to +VREFIN] for 4/2 fully differential input channels depending on the setting of bit RANGE (page 14) and SE/FDN (page 14). For the [0V to 2 x VREFIN] mode, the device must be operated from a 4.75 to 5.25V supply. The AS1543/44 provides flexible power management options (see bits PM1, PM0 (page 14) of the control register) for the best power performance for a given throughput rate. Converter Operation The AS1543/44 is a 12-bit successive approximation analog-to-digital converter based around a capacitive DAC. The AS1543/44 can convert analog input signals in the range [0V to VREFIN] or [0V to 2 x VREFIN] or [-VREFIN/2 to +VREFIN/2] or [-VREFIN to +VREFIN] . Figure 21 and Figure 22 show simplified diagrams of the ADC operation. The ADC circuitry is made up of control logic, SAR, and a capacitive DAC, which are used to redistribute fixed amounts of charge with the capacitive DAC to bring the comparator back into a balanced condition. Figure 21 shows the ADC during its acquisition phase. Sample switch and input switch are closed. The comparator is held in a balanced condition and the sampling capacitors CHOLD acquires the signal on the selected VINx channel. Figure 21. Data Acquisition When a conversion is started (see Figure 22), sample switch and input switch opens causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to redistribute fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is re-balanced, the conversion is complete. Control logic generates the ADC output code. See page 16 for the ADC transfer functions. + – + Comparator RIN CSWITCH 11pF CHOLD 13pF – CH0 CH1 CH2 CH3 CH4 CH5 CH7 AGND REFIN AIN+ CSWITCH 11pF + CHOLD 13pF – Sample Switch CSWITCH includes all parasitics Analog Input Multiplexer AIN- Input Switch Input Switch AGND S&H and capacitive DAC Control Logic |
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