STM32F100V8H7B datasheet(66/84 Pages) STMICROELECTRONICS

66 / 84 page

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

66/84

Doc ID 16455 Rev 2

Equation 1: RAIN max formula:

Table 41.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

VREF+

Positive reference voltage

2.4

VDDA

IVREF

Current on the VREF input

160(1)

220(1)

µA

fADC

ADC clock frequency

0.6

MHz

(2)

Sampling rate

0.05

MHz

fTRIG

(2)

External trigger frequency

fADC = 12 MHz

823

kHz

1/fADC

VAIN

(3)

Conversion voltage range

0 (VSSA tied to

ground)

VREF+

RAIN

(2)

External input impedance

See Equation 1 and

Table 42 for details



RADC

(2)

Sampling switch resistance



CADC

(2)

Internal sample and hold

capacitor

8pF

tCAL

(2)

Calibration time

fADC = 12 MHz

5.9

µs

1/fADC

tlat

(2)

Injection trigger conversion

latency

fADC = 12 MHz

0.214

µs

3(4)

1/fADC

tlatr

(2)

Regular trigger conversion

latency

fADC = 12 MHz

0.143

µs

2(4)

1/fADC

(2)

Sampling time

fADC = 12 MHz

0.125

17.1

µs

1.5

239.5

1/fADC

tSTAB

(2)

Power-up time

µs

tCONV

(2)

Total conversion time

(including sampling time)

fADC = 12 MHz

1.17

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

Based on characterization results, not tested in production.

Guaranteed by design, not tested in production.

In devices delivered in LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.

Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally connected to VSSA),

see Table 4: STM32F100xx pin definitions and Figure 6.

For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.

AIN

ADC





--------------------------------------------------------------

ADC

–



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