STM32F100V8H7B datasheet(34/84 Pages) STMICROELECTRONICS

34 / 84 page

Electrical characteristics

STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB

34/84

Doc ID 16455 Rev 2

5.3

Operating conditions

5.3.1

General operating conditions

Table 6.

Current characteristics

Symbol

Ratings

Max.

Unit

IVDD

Total current into VDD/VDDA power lines (source)

(1)

All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power

supply, in the permitted range.

150

IVSS

Total current out of VSS ground lines (sink)

(1)

150

IIO

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

25

IINJ(PIN)

(2)(3)

IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum

cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive

injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.

Negative injection disturbs the analog performance of the device. See note in Section 5.3.16: 12-bit ADC

characteristics.

Injected current on NRST pin

± 5

Injected current on High-speed external OSC_IN and Low-

speed external OSC_IN pins

± 5

Injected current on the PA5 and PA6 pins(4)

+5 / –0

Injected current on any other pin(4)

When several inputs are submitted to a current injection, the maximum

I

INJ(PIN) is the absolute sum of the

positive and negative injected currents (instantaneous values). These results are based on

characterization with

I

INJ(PIN) maximum current injection on four I/O port pins of the device.

± 5

I

INJ(PIN)

(2)

Total injected current (sum of all I/O and control pins)(4)

± 25

Table 7.

Thermal characteristics

Symbol

Ratings

Value

Unit

TSTG

Storage temperature range

–65 to +150

°C

Maximum junction temperature

150

°C

Table 8.

General operating conditions

Symbol

Parameter

Conditions

Min

Max

Unit

fHCLK

Internal AHB clock frequency

MHz

fPCLK1

Internal APB1 clock frequency

fPCLK2

Internal APB2 clock frequency

VDD

Standard operating voltage

3.6

VDDA

(1)

Analog operating voltage

(ADC not used)

Must be the same potential

as VDD

23.6

Analog operating voltage

(ADC used)

2.4

3.6

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