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STM32F100V8H7B 数据表(PDF) 50 Page - STMicroelectronics |
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STM32F100V8H7B 数据表(HTML) 50 Page - STMicroelectronics |
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50 / 84 page  Electrical characteristics STM32F100x4, STM32F100x6, STM32F100x8, STM32F100xB 50/84 Doc ID 16455 Rev 2 5.3.8 PLL characteristics The parameters given in Table 26 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. tWUSTOP (1) Wakeup from Stop mode (regulator in run mode) 3.6 µs Wakeup from Stop mode (regulator in low-power mode) 5.4 tWUSTDBY (1) Wakeup from Standby mode 50 µs 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. Table 25. Low-power mode wakeup timings (continued) Symbol Parameter Typ Unit Table 26. PLL characteristics Symbol Parameter Value Unit Min(1) Typ Max(1) 1. Based on device characterization, not tested in production. fPLL_IN PLL input clock(2) 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 18.0 24 MHz PLL input clock duty cycle 40 60 % fPLL_OUT PLL multiplier output clock 16 24 MHz tLOCK PLL lock time 200 µs Jitter Cycle-to-cycle jitter 300 ps |
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