MMA5206WR2 datasheet(21/61 Pages) FREESCALE

21 / 61 page

Sensors

Freescale Semiconductor

MMA52xxWR

Preliminary

3.3.3

VBUF, VREG, and VREGA Capacitance Monitor

A monitor circuit is incorporated to ensure predictable operation if the connection to the external VBUF, VREG, or VREGA, ca-

pacitor becomes open.

In asynchronous mode, the VBUF regulator is disabled tCAPTEST_ADLY seconds after each data transmission for a duration of

tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold,

forcing a device reset.

In synchronous mode, the VBUF regulator is disabled tCAPTEST_SDLY seconds after each sync pulse for a duration of

tCAPTEST_TIME seconds. If the external capacitor is not present, the regulator voltage will fall below the internal reset threshold,

forcing a device reset.

The VREG and VREGA regulators are disabled at a continuous rate (tCAPTEST_RATE), for a duration of tCAPTEST_TIME seconds.

If either external capacitor is not present, the associated regulator voltage will fall below the internal reset threshold, forcing a

device reset.

Figure 10. VBUF Capacitor Monitor - Asynchronous Mode

Figure 11. VBUF Capacitor Monitor - Synchronous Mode

CAP_Test

VBUF

Time

Capacitor Present

VBUF_UV_f

POR

Capacitor Open

tCAPTEST_TIME

IDATA

tCAPTEST_ADLY

CAP_Test

VBUF

Time

Capacitor Present

VBUF_UV_f

POR

Capacitor Open

tCAPTEST_TIME

VCC

tCAPTEST_SDLY

tTRIG

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