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MMA5206WR2 数据表(PDF) 46 Page - Freescale Semiconductor, Inc |
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MMA5206WR2 数据表(HTML) 46 Page - Freescale Semiconductor, Inc |
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46 / 61 page ![]() Sensors 46 Freescale Semiconductor MMA52xxWR Preliminary 4.5.3 16-Bit Resolution Mode The device can be programmed to respond in 16-bit Resolution Mode by setting the TRANS_MD[1:0] bits to “16-bit Resolution Mode”. In this mode, the 26 bit digital output from the DSP is clipped and scaled to a 16-bit word. Figure 38 shows the method used to establish the 16-bit data word from the 26 bit DSP output. Figure 38. 16-Bit Output Scaling Diagram 16-Bit Resolution Mode can be programmed to operate in either “Simultaneous Sampling Mode”, or “Synchronous Sampling Mode”, by setting the LATENCY bit to the desired operating mode. In Simultaneous Sampling Mode, the most recent interpolated acceleration data sample is latched at tTRIG (rising edge of Sync Pulse). In Synchronous Sampling Mode, the most recent inter- polated acceleration data sample is latched at the time programmed in TIMESLOTA[9:0], relative to tTRIG (rising edge of Sync Pulse). The most significant 10 bits (D[21:12]) are truncated and transmitted starting at the time programmed in TIMESLOTA[9:0], rel- ative to tTRIG. The 16-bit value is then clipped to ±480 counts, and the least significant 10 bits (D15:D6) are transmitted starting at the time programmed in TIMESLOTB[9:0], relative to tTRIG. When 16-Bit Resolution Mode is enabled, PSI5 Initialization data is transmitted in both TIMESLOTA[9:0] and TIMESLOTB[9:0]. Identical data is transmitted in both Time slots, including the 10-Bit Resolution Raw Offset and Self-Test Data in Field 9, D27 though D31 if enabled. Figure 39. 16-Bit Resolution Mode with Synchronous Sampling Note: In the event that the programmed values in TIMESLOTA [9:0] and TIMESLOTB[9:0] result in a conflict, no data will be transmitted in TIMESLOTB [9:0]. Over Range Signal Noise Margin D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 ... D2 D1 D0 16-bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Using Rounding ≤tLAT_INTERP + tDATASETUP_16 tTIMESLOTA tTIMESLOTB |
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