MMA5206WR2 datasheet(10/61 Pages) FREESCALE

10 / 61 page

Sensors

Freescale Semiconductor

MMA52xxWR

Preliminary

2.8

Dynamic Electrical Characteristics - Supply and SPI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified

1. Parameters tested 100% at final test.

2. Parameters tested 100% at wafer probe.

3. Verified by characterization

4. * Indicates critical characteristic.

5. Verified by qualification testing.

6. Parameters verified by pass/fail testing in production.

7. Functionality verified 100% via boundary scan. (Timing is directly determined by internal oscillator frequency.)

8. N/A.

9. Guaranteed by design.

10. N/A.

11. Measured at VCC pin; VSYNC guaranteed across full VIDLE range.

12. Self-Test repeats on failure up to a ST_RPTMAX times before transmitting Sensor Error Message

13. N/A.

14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.

15. Filter cut-off frequencies are directly dependent upon the internal oscillator frequency.

Characteristic

Symbol

Min

Typ

Max

Units

175

Quiescent Current Settling Time (Power Applied to Iq = IIDLE +/- 2mA)

tSET

⎯⎯

5ms

(3)

176

Reset Recovery Internal Delay (After internal POR)

tINT_INIT

⎯

16000 / fOSC

⎯

s(7)

177

178

179

VCC Micro-cut (CBUF=CREG=CREGA=1μF)

Survival Time (Vcc disconnect without Reset,

CBUF=CREG=CREGA=700nF)

Survival Time (Vcc disconnect without Reset, CBUF=CREG=CREGA=1μF)

Reset Time (Vcc disconnect above which Reset is guaranteed)

tVCC_MICROCUTmi

tVCC_MICROCUT

tVCC_RESET

⎯

1000

μs

(3)

180

181

182

183

VBUF, Capacitor Monitor Disconnect Time (Figure 10)

POR to first Capacitor Test Disconnect

Disconnect Time (Figure 10)

Disconnect Delay, Asynchronous Mode (Figure 10)

Disconnect Delay, Synchronous Mode (Figure 11)

tPOR_CAPTEST

tCAPTEST_TIME

tCAPTEST_ADLY

tCAPTEST_SDLY

⎯

12000/fOSC

6 / fOSC

688 / fOSC

72 / fOSC

⎯

(7)

184

185

186

VREG, VREGA Capacitor Monitor

POR to first Capacitor Test Disconnect

Disconnect Time

Disconnect Rate

tPOR_CAPTEST

tCAPTEST_TIME

tCAPTEST_RATE

⎯

12000 / fOSC

6 / fOSC

256 / fOSC

⎯

(7)

187

188

189

190

191

192

193

194

195

196

197

198

199

200

Serial Interface Timing (See Figure 7, CDOUT ≤ 80pF, RDOUT ≥ 10kΩ)

Clock (SCLK) period (10% of VCC to 10% of VCC)

Clock (SCLK) high time (90% of VCC to 90% of VCC)

Clock (SCLK) low time (10% of VCC to 10% of VCC)

Clock (SCLK) rise time (10% of VCC to 90% of VCC)

Clock (SCLK) fall time (90% of VCC to 10% of VCC)

CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)

CS asserted to DOUT valid (CS = 10% of VCC to DOUT = 10/90% of VCC)

Data setup time (DIN = 10/90% of VCC to SCLK = 10% of VCC)

DIN Data hold time (SCLK = 90% of VCC to DIN = 10/90% of VCC)

DOUT Data hold time (SCLK = 90% of VCC to DOUT = 10/90% of VCC)

SCLK low to data valid (SCLK = 10% of VCC to DOUT = 10/90% of VCC)

SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)

CS high to DOUT disable (CS = 90% of VCC to DOUT = Hi Z)

CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)

tSCLK

tSCLKH

tSCLKL

tSCLKR

tSCLKF

tLEAD

tACCESS

tSETUP

tHOLD_IN

tHOLD_OUT

tVALID

tLAG

tDISABLE

tCSN

320

120

⎯

1000

⎯

(9)

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