MMA5206WR2 datasheet(30/61 Pages) FREESCALE

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Sensors

Freescale Semiconductor

MMA52xxWR

Preliminary

Figure 21. 0.1 Hz Offset Cancellation Low Pass Filter Characteristics

3.5.3.4

Offset Monitor

The device includes an offset monitor circuit. The output of the single pole low pass filter in the offset cancellation block is

continuously monitored against the offset limits specified in Section 2.4. An up/down counter is employed to count up If the output

exceeds the limits, and to count down if the output is within the limits. The output of the counter is compared against the count

limit OFFMONCNTLIMIT. If the counter exceeds the limit, the OFF_B flag in the SC register is cleared. The counter rails once the

max counter value is reached (OFFMONCNTSIZE). The offset monitor is disabled during Initialization Phase1, Phase 2, and

Phase 3.

3.5.3.5

Data Interpolation

The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital

signal processing chain is delayed one sample time. On detection of a sync pulse the transmitted data is interpolated from the

2 previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample time. Reference

Section 4.5 for more information regarding interpolation and data latency.

3.5.3.6

Output Scaling

The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-bit word which spans the acceleration range of the

device. Figure 22 shows the method used to establish the output acceleration data word from the 26-bit DSP output.

Figure 22. 10-Bit Output Scaling Diagram

Over Range

Signal

Noise

Margin

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

...

8-bit Data Word

D21

D20

D19

D18

D17

D16

D15

D14

Using Rounding

10-bit Data Word

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

Using Rounding

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