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WM9708 数据表(PDF) 8 Page - Wolfson Microelectronics plc

部件名 WM9708
功能描述  AC97 Revision 2.1 Audio Codec
PDF  28 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM9708 数据表(HTML) 8 Page - Wolfson Microelectronics plc

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WM9708
Advanced Information
WOLFSON MICROELECTRONICS LTD
AI Rev 2.0 April 2001
8
WARM RESET
SYNC
BITCLK
t
SYNC_HIGH
t
SYNC2CLK
Figure 3 Warm Reset Timing
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
SYNC active high pulse width
tSYNC_HIGH
1.3
µs
SYNC release (or falling edge) to
BITCLK startup delay
tSYNC2_CLK
162.4
ns
CLOCK SPECIFICATIONS
BITCLK
SYNC
t
CLK_HIGH
t
CLK_LOW
t
CLK_PERIOD
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC_PERIOD
Figure 4 Clock Specifications (50pF External Load)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
BITCLK frequency
12.288
MHz
BITCLK period
tCLK_PERIOD
81.4
ns
BITCLK output jitter
750
ps
BITCLK high pulse width
(See Note)
tCLK_HIGH
32.56
40.7
48.84
ns
BITCLK low pulse width
(See Note)
tCLK_LOW
32.56
40.7
48.84
ns
SYNC frequency
48.0
kHz
SYNC period
tSYNC_PERIOD
20.8
µs
SYNC high pulse width
tSYNC_HIGH
1.3
µs
SYNC low pulse width
tSYNC_LOW
19.5
µs
Note: Worst case duty cycle restricted to 40/60.



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