WM9708

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 2.0 April 2001

14

When the Codec is a slave device, bits 14 and 13 are not used to validate data in slots 1 and 2.

Instead, if the message ID bits (1:0) match the Codec ID then the address is valid and bit 19 from

slot 1 then indicates if slot 2 is valid.

SYNC

BIT_CLK

SDATA_OUT

VALID

FRAME

SLOT (1)

SLOT (2)

WM9707 SAMPLES

SYNC ASSERTION HERE

WM9707 SAMPLES

FIRST SDATA_OUT

BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

Figure 10 Start of an Audio Output Frame

A new audio output frame begins with a low to high transition of SYNC as shown in Figure 10. SYNC

is synchronous to the rising edge of BITCLK. On the immediately following falling edge of BITCLK,

the WM9708 samples the assertion of SYNC. This falling edge marks the time when both sides of

AC-link are aware of the start of a new audio frame. On the next rising edge of BITCLK, AC’97

transitions SDATAOUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is

presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the WM9708 on the

following falling edge of BITCLK. This sequence ensures that data transitions and subsequent

sample points for both incoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a fixed

48ks/s on the AC’97 controller. This requirement is necessary to ensure that interoperability between

the AC’97 controller and the WM9708, among other things, can be guaranteed by definition for

baseline specified AC’97 features.

SDATAOUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions

stuffed with 0s by the AC’97 controller.

In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97

controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.